Design Verification Engineer (5-20 Years)

Company Description

SILCOSYS Solutions Pvt Ltd. collaborates with clients in developing cutting-edge technologies for flagship product lines across various industries, including mobile devices, routers/switches, consumer goods, and microprocessors. The company excels in designing intricate SoCs and boasts one of the industry's most robust analog/mixed signal and software design teams.

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We are seeking a highly skilled Senior Design Verification Engineer to join our dynamic team in Bangalore. You will be responsible for verifying complex SoC/IP designs using advanced verification methodologies. The ideal candidate will have a strong background in SystemVerilog/UVM, a deep understanding of digital design, and experience in building robust verification environments.

Key Responsibilities:

• Develop and execute verification plans for IP/SoC level designs.
• Create reusable testbenches using SystemVerilog and UVM.
• Write and maintain functional coverage and assertions.
• Collaborate with design, architecture, and firmware teams to ensure comprehensive verification.
• Debug test failures and work closely with RTL designers to resolve issues.
• Contribute to methodology improvements and mentor junior engineers.

Requirements:

• Bachelor's or Master's degree in Electronics/Electrical/Computer Engineering.
• 5+ years of experience in Design Verification.
• Strong proficiency in SystemVerilog, UVM, and scripting languages (Perl/Python/Tcl).
• Solid understanding of digital design concepts and simulation tools (e.g., VCS, Questa).
• Experience with coverage-driven and constraint-random verification.
• Excellent problem-solving and communication skills.

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