Design Engineer

Tessolve is looking for an experienced Physical Design Engineer to join our team in Bangalore. The ideal candidate will have a strong background in RTL to GDSII implementation, expertise in advanced process nodes, and hands-on experience with industry-standard tools for floor planning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.

Key Responsibilities:

End-to-end physical design flow from RTL to GDSII at advanced technology nodes (7nm, 5nm, or below).

Floor planning and Partitioning: Optimize chip area, power, and performance.

Placement and CTS: Optimize standard cell placement, buffer insertion, and clock tree synthesis.

Routing and Timing Closure: Work on congestion analysis, RC extraction, and static timing analysis (STA).

Power Optimization: Implement low-power techniques such as clock gating, power gating, and multi-voltage domains.

Physical Verification: Perform DRC, LVS, and Antenna checks using industry-standard tools.

Sign-off Analysis: Work on IR drop, Electro migration (EM), and Signal Integrity (SI) analysis.

Collaborate with RTL design, DFT, and verification teams for design convergence.

Debug and resolve timing, power, and physical verification issues.

Required Skills:

3 to 8 years of experience in Physical Design and Implementation.

Strong knowledge of EDA tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or Mentor Olympus).

Experience in floor planning, power planning, placement, routing, and timing closure.

Expertise in Static Timing Analysis (STA) using Primetime or Tempus.

Hands-on experience in physical verification tools (Calibre, PVS, or Pegasus).

Good understanding of design constraints, clock tree optimization, IR drop, and power integrity.

Experience with scripting (Tcl, Perl, Python) for automation is a plus.

Strong problem-solving skills and ability to work in a fast-paced environment.

Preferred Qualifications:

Experience with 7nm, 5nm, or lower process nodes.

Knowledge of low-power design methodologies.

Familiarity with multi-power domain design (UPF/CPF-based flows).

Why Join Tessolve

Opportunity to work on cutting-edge semiconductor technology.

Exposure to advanced process nodes and complex designs.

Collaborative and innovative work environment.

Competitive salary and benefits.