ASIC DIGITAL DESIGN ENGINEER

As a Senior Design/Verification - Subsystems Lead at Synopsys, you will be part of the Digital IP Subsystem team that has experienced significant growth. We are seeking talented engineers to join us in Bangalore/Hyderabad, India and be a part of our exciting journey in the SysMoore era. **Design Lead:** In the role of an RTL Design lead, you will experience the thrill of achieving bug-free RTL from requirements or specifications. Your expertise in driving the design effort for complex IP/Subsystem/SoC blocks, with a track record of multiple tape-outs, will be invaluable in delivering high-quality results. **Verification Lead:** As a Verification lead, you will enjoy the challenge of identifying and rectifying bugs to ensure the design intent is realized. Your role is critical in ensuring the flawless operation of chips, such as those on space telescopes capturing stunning images of galaxies. Your experience in leading multiple tape-outs and closing verifications of complex IP/Subsystem/SoC blocks will be instrumental in our success. **Design role:** In the position of a Senior RTL Subsystems Designer Lead with over 8 years of experience, you will be responsible for driving the Subsystem life cycle from requirements to final release phases. This includes crafting functional specifications, defining micro-architectures, coding RTL using best practices, conducting RTL quality checks, collaborating with Verification and implementation teams, and overseeing project completion. Proficiency in standard protocols like PCIe, DDR, UFS, USB, AMBA, as well as hands-on experience in low power design and understanding of DFT requirements and architecture are essential. Your ability to work effectively with cross-functional teams will be crucial in delivering successful projects. **Verification role:** In the role of a Senior Verification lead with over 8 years of experience, you will lead the complete Verification cycle by crafting test plans, architecting verification environments, developing test infrastructure, and executing plans to closure with coverage. Proficiency in Functional Verification of standard protocols like PCIe, DDR, UFS, USB, AMBA, as well as power-aware Verification with UPF, is required. Hands-on experience in Gate Level Verification is a valuable addition. Your collaboration with cross-functional teams will be key to driving projects to completion.,