Analog Layout Engineer

Job Title

Custom Analog Layout Engineer

Exp-56 Years

Advanced Nodes (N3/N5/Samsung 4)

Location

BLR/Ahmedabad/Mumbai

Role Summary

hands-on Custom Analog Layout Engineer

Key Responsibilities

• Create

  full-custom layout

  for high-speed and precision analog/RF blocks: LDOs, bandgaps, PLL/ADPLL, SerDes/RX front-end slices (as applicable), ADC/DAC analog, comparators, references, filters, IO analog, ESD-aware custom structures.
• Drive

  floorplanning, device placement, routing, shielding

  , and

  parasitic optimization

  for performance (noise, matching, bandwidth, stability).
• Execute and optimize

  matching-critical structures

  : common-centroid, interdigitated devices, dummy strategies, gradient mitigation, symmetrical routing, guard rings, deep n-well isolation.
• Implement

  high-speed routing techniques

  : controlled impedance (when required), capacitance management, return paths, coupling/noise isolation, and clock/jitter-sensitive routing practices.
• Own layout signoff closure:

  DRC/LVS

  , density/fill, antenna, ERC,

  PERC/ESD checks

  (as required), EM/IR constraints awareness, and

  PEX review

  with designers.
• Collaborate with circuit design to

  close post-layout performance

  (gain/phase margin, bandwidth, jitter, SNR/SFDR, offset/noise, RF metrics) and iterate quickly.
• Support

  tapeout readiness

  : layout reviews, checklist compliance, documentation, and integration with top-level/chiplet/SoC assembly teams.
• Contribute to layout

  best practices

  and reusable templates for advanced-node layout efficiency (while remaining hands-on).

Required Qualifications

• 5–6 years

  of direct, hands-on

  custom analog layout

  experience (no managerial requirement).
• Demonstrated experience in

  advanced process nodes

  :

  TSMC N5/N3

  and/or

  Samsung 4nm

  (tapeout or near-tapeout experience strongly preferred).
• Solid experience with

  RF / high-speed analog layout

  constraints: isolation, coupling control, shielding, matching, and parasitic management.
• Strong understanding of:

• Matching and symmetry

  techniques and their impact on circuit performance

• Noise coupling

  (substrate/PSRR/grounding), guard rings, well isolation, deep n-well strategies

• Parasitics

  and tradeoffs (R/C effects, coupling, corner sensitivity)
• Proficiency with industry layout tools (one or more):

  Cadence Virtuoso

  (Layout XL/GXL), Calibre/Assura/PVS flows, and standard verification workflows.
• Ability to work from schematics/netlists and

  independently drive closure

  with minimal supervision.

Preferred Qualifications (Nice to Have)

• Experience with

  FinFET layout practices

  (device quantization, routing constraints, metal stack awareness).
• Familiarity with

  RF layout best practices

  (inductors/transformers, transmission-line thinking, sensitive node isolation).
• Experience supporting

  chiplet/SoC integration

  (top-level assembly, bump planning, block interfaces, hierarchical LVS).
• Knowledge of reliability checks (EM/IR, latch-up considerations, ESD-aware layout, antenna fixes).
• Scripting/automation exposure (SKILL/Tcl/Python) for layout productivity (optional).

What Success Looks Like

• Delivers high-quality layouts that pass

  DRC/LVS/PEX

  with minimal rework.
• Produces layout that enables circuit teams to meet

  performance targets

  on advanced nodes.
• Communicates clearly, flags risks early, and iterates quickly toward tapeout.