Essential Skills: Ability to develop new software architecture and good leadership skills, Strong hands-on experience in C/C++ based software development, Strong background in Design Patterns, Data Structure, Algorithms, and programming concepts, Familiarity with multi-threaded and distributed code development, Familiarity with ASIC design flow and the EDA tools and methodologies used therein, Good knowledge of Verilog, SystemVerilog & VHDL HDL Well versed with Software Engineering and development processes Experience of production code development on Unix/Linux platforms, Exposure to developer tools such as gdb, Valgrind Exposure with source code control tool like Perforce, Good analysis and problem-solving skills, Desirable Skills: Work experience in Synthesis tools Work experience in EDA Experience in technically leading significant size projects Personal Attributes: Highly enthusiastic and energetic team player with the ability to go an extra mile, Good written and verbal communication skills, Strong desires to learn and explore new technologies,

You are a highly skilled AI Engineer passionate about transforming IT workflows into intelligent, agentic processes. Your expertise in Python, AI-driven IT automation, and IT infrastructure allows you to design and implement scalable and reliable AI-driven workflows that enhance IT operations. You thrive in collaborative environments, working closely with MLOps teams to ensure seamless deployment and optimization of AI solutions. Your ability to analyze and decompose complex IT workflows enables you to identify automation opportunities and create efficient, autonomous systems. With a strong focus on reliability and scalability, you ensure that AI-driven automation aligns with enterprise IT best practices and operates efficiently across cloud and hybrid IT environments. Your experience with ITSM platforms such as ServiceNow, BMC, or Jira, along with your knowledge of Kubernetes, Docker, and CI/CD pipelines, makes you an ideal candidate to lead the transformation of IT workflows into intelligent, self-sustaining AI-driven processes. What You ll Be Doing: Analyze and decompose IT workflows, identifying automation opportunities using agentic AI. Implement autonomous AI-driven workflows for incident management, self-healing systems, and intelligent service operations. Fine-tune AI models and develop prompt engineering strategies for optimized performance. Develop and maintain robust, scalable AI-powered IT workflows. Ensure AI-driven automation is fault-tolerant, efficient, and aligned with enterprise IT best practices. Work closely with IT teams to integrate AI workflows into existing operational frameworks. Partner with MLOps engineers to deploy, monitor, and optimize AI-driven workflows in production. Continuously improve deployed models through feedback loops and real-world performance tuning. Use Python to develop automation scripts, AI workflow integrations, and API-driven IT solutions. Work with Kubernetes, Terraform, and CI/CD pipelines to ensure automated deployment and lifecycle management. The Impact You Will Have: Transform IT workflows into intelligent, agentic AI-driven processes. Enhance IT service efficiency through AI-driven incident resolution, self-healing systems, and workflow automation. Optimize IT operations by predicting, preventing, and resolving IT issues proactively. Ensure scalable AI deployment using Python, Kubernetes, and CI/CD for production-ready AI workflows. Reduce costs and improve reliability by minimizing downtime and optimizing resource usage with AI-powered automation. Enable self-healing IT systems and predictive issue resolution. What You ll Need: Strong expertise in Python for scripting, API development, and IT automation. Experience in agent-based AI frameworks and autonomous workflow orchestration. Familiarity with ITSM platforms such as ServiceNow, BMC, or Jira. Hands-on experience with Kubernetes, Docker, and cloud automation tools. Experience working closely with MLOps teams to deploy and scale AI-driven IT automation.

What You ll Be Doing: Develop and implement layout designs for A&MS integrated circuits. Optimize layouts using industry-standard EDA tools. Perform physical verification and design rule checks. Participate in Layout reviews and provide feedback. Collaborate with circuit designers on specifications and constraints. Enhance layout design methodologies and best practices. Stay updated with industry trends in A&MS layout design. The Impact You Will Have: Ensure high quality and performance of A&MS integrated circuits. Drive innovation with cutting-edge layout designs. Improve manufacturability and reliability through meticulous design. Contribute valuable feedback during design reviews. Foster continuous improvement in design methodologies. Mentor junior engineers by sharing your expertise.

You are an innovative and analytical thinker with a passion for technology and a drive to solve complex engineering challenges You thrive in a collaborative environment, working alongside a high-caliber team of engineers to develop technical solutions that push the boundaries of AI-driven optimization You possess a strong foundation in computer science or electronics, with a deep understanding of C/C++ and Linux Your excellent communication skills enable you to effectively convey ideas and work seamlessly with product engineers to define and solve problems You are committed to continuous improvement, always seeking ways to enhance performance and quality in your work Your ability to debug issues, optimize algorithms, and develop new features makes you an invaluable asset to any engineering team, What Youll Be Doing: Developing SignOff ECO optimization algorithms and heuristics, Debugging issues related to design loading and timing/power optimization, Striving for continuous improvements in QoR to achieve faster timing convergence with optimal power overhead, Collaborating with a team of engineers to develop technical solutions to complex problems, Communicating with product engineers to understand and define problem scope, Ensuring strict performance and quality requirements are met, The Impact You Will Have: Enhancing the performance and efficiency of PrimeClosure, the industry's first AI-driven signoff ECO solution, Contributing to the development of cutting-edge algorithms that optimize timing and power in chip design, Improving the overall quality and reliability of our products through rigorous debugging and testing, Driving innovation and continuous improvement in our engineering processes, Supporting customer success by resolving issues and implementing new features based on their feedback, Helping shape the future of AI-driven optimization in the semiconductor industry, What Youll Need: A degree in Computer Science or Electronics, 5+ years of experience in relevant field Strong analytical and problem-solving skills, Proficiency in C/C++ and Linux, Excellent communication and teamwork abilities, A passion for technology and innovation, Who You Are: A collaborative team player who thrives in a dynamic and innovative environment, A proactive and self-motivated individual with a strong attention to detail, An excellent communicator who can articulate complex ideas clearly and effectively, A creative thinker who is always looking for new ways to solve problems and improve processes, A dedicated professional committed to delivering high-quality work, The Team Youll Be A Part Of: You will be part of the PrimeClosure R&D team, responsible for developing and maintaining the industry's first AI-driven signoff ECO solution, PrimeClosure This team is dedicated to pushing the boundaries of technology and innovation, working collaboratively to develop cutting-edge solutions that address complex engineering challenges Together, you will strive for continuous improvements in performance and quality, ultimately shaping the future of AI-driven optimization in the semiconductor industry, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

As an ideal candidate, you are a highly motivated and experienced Analog Design Engineer with a passion for developing state-of-the-art analog sensors. You have a solid background in custom analog/mixed-signal circuit design, circuit simulations, custom layout, and post-silicon characterization. You thrive in a collaborative environment, guiding junior engineers, and liaising with layout teams to achieve optimal engineering solutions. Your forward-thinking approach, combined with your extensive technical knowledge, enables you to tackle the unique challenges posed by various target applications. You possess a BTech or MTech degree in Electrical Engineering with 1+ years of relevant industry experience or a PhD with relevant experience. Your expertise in advanced process challenges, including ESD and reliability, and your familiarity with tools like PrimeSim, FineSim, and HSPICE, set you apart as a leader in the field. What You'll Be Doing: Conceptualizing, designing, and productizing state-of-the-art on-chip Process, Voltage, Temperature, Current, and Droop sensors. Developing innovative solutions in the field of on-die monitoring. Liaising with the layout team to achieve the best possible engineering solutions. Deploying new sensors into test chips and conducting post-silicon characterization. Guiding and mentoring junior engineers and tracking their work progress. Collaborating with internal teams and external customers to ensure project success. The Impact You Will Have: Enhancing the performance, power, area, schedule, and yield of our products. Contributing to the reliability and optimization of next-generation intelligent in-chip sensors. Driving innovation in on-die monitoring solutions. Improving the integration process for customers, leading to faster time-to-market. Providing technical leadership and mentoring to junior engineers. Ensuring the successful deployment and characterization of new sensors. What You'll Need: Strong technical experience in full custom analog/mixed-signal circuit design, simulations, and custom layout. Technical knowledge of custom Analog/AMS design techniques, implementation, and verification. Familiarity with advanced process challenges, including ESD and reliability. Experience with tools like PrimeSim, FineSim, HSPICE, and Custom Compiler or equivalent schematic layout editor tools.

What You ll Be Doing: Leading and managing IP design and development projects from initiation through to delivery. Coordinating with cross-functional teams to ensure project milestones and deliverables are met on time. Engaging with external SOC customers to understand their requirements and ensure their needs are met. Presenting project status updates and reports to senior management and stakeholders. Ensuring adherence to quality standards and regulatory requirements throughout the project lifecycle. Driving continuous improvement initiatives within the program management processes. The Impact You Will Have: Ensuring the successful delivery of high-quality IP products that meet customer expectations. Contributing to the strategic goals of Synopsys by effectively managing complex projects. Enhancing cross-functional collaboration and communication within the organization. Driving innovation in IP design and development through effective program management. Building strong relationships with external SOC customers, enhancing customer satisfaction and loyalty. Improving the efficiency and effectiveness of program management processes and practices. What You ll Need: 15+ years of experience in IP design or management in multiple process technologies up to 3nm. Experience in IP program management or working with cross-functional teams. Experience in working with external SOC customers and presenting to senior management. Knowledge of SOC design and architecture, product qualification, signal and power integrity, and package design. BS or MS degree in Electrical or Computer Engineering

You Are: You are a skilled Emulation R&D Engineer with over 8 years of experience and a strong academic background in Electronic & Communication or Computer Science Engineering. Your expertise in C/C++, OOPS, and HDL languages like System Verilog and Verilog, along with your scripting skills in Perl or TCL, make you a valuable team member. You possess knowledge of protocols such as ENET, HDMI, MIPI, AMBA, and UART, and have experience with UVM and Functional Verification. You are a resourceful problem-solver, a team player, and have excellent communication skills. What You ll Be Doing: Designing and developing emulation models. Implementing and verifying digital designs using System Verilog and Verilog. Developing scripts in Perl, TCL, or other languages. Collaborating with cross-functional teams. Conducting protocol verification for various standards. Utilizing UVM for design validation. The Impact You Will Have: Enhancing emulation model efficiency. Contributing to high-performance silicon chips. Improving design reliability through verification. Streamlining workflows with automation. Ensuring protocol compliance. Driving technological advancements. What You ll Need: B.E / M.E. in Electronic & Communication / Computer Science Engineering. Proficiency in C/C++ and OOPS. Knowledge of digital design and HDL languages. Experience with scripting languages. Familiarity with multiple protocols likeethernet, pcie, cxl, CSI, DSI, UFS AMBA, CHIand UVM. Who You Are: Effective communicator. Team player. Resourceful and detail-oriented. Innovative problem-solver. Adaptable learner.

Looking forward towork on conceptualizing, designing and productizing state of the art Monitor IP to be used in SLM monitors realized though ASIC design flow. Work on Architecting sensing elements for on-chip Process, Voltage, Temperature, glitch and Droop monitors for monitoring silicon biometrics. You will be the part of SLM team. Individual should have strong technical experience in full custom mixed-signal circuit design, circuit simulations, working knowledge of custom layout, and pre-post-silicon characterization. Additional responsibilities include: Development of statistical simulation methodologies. Liaising with layout team to achieve best possible design solution. End to end ownership of the designed custom cells. Deployment of new circuits into test chips and post-silicon characterization Architecting new sensors and enhancing existing ones through collaboration with other architects and stakeholders. Building and refining design flows to enhance efficiency and effectiveness. Conducting pre and post-layout simulations and characterization across various design corners. Ensuring designs meet advanced finfet / GAA reliability and aging, reliability and Automotive grade requirements Working closely with the RTL, Verification and Physical Design teams for ensuing integration and Quality. Owning the product from Spec to Silicon report. Preferred skills: Strong custom design experience - specification, circuit design description and schematics. Strong understanding of device Physics and Can work independently and debug and provide circuit solutions. Hands on experience with circuit design & simulation tools, IC design CAD packages - from any EDA vendor Strong understanding of SPICE simulator concepts and simulation methods Familiar with circuit simulation tools like PrimeSim, FineSim, HSPICE or similar Must have prior experience with Custom Compiler or equivalent schematic & Layout editor tools Experience with statistical design methodology like generating and analyzing Monte-Carlo results Awareness of post-layout extraction & simulation, testing in conjunction with silicon validation Demonstrated technical expertise in the productization of advanced technologies.

What You ll Be Doing: Implementing state-of-the-art Verification environments for the DesignWare family of synthesizable cores. Performing Verification tasks for IP cores, focusing on domains such as USB, PCI Express, Ethernet, and AMBA. Collaborating closely with the RTL design team and other expert Verification Engineers globally. Engaging in Test planning, Test environment coding at both unit and system levels, Test case coding, and debugging. Coding and analyzing functional coverage and meeting quality metric goals. Managing regression processes to ensure comprehensive verification. The Impact You Will Have: Enhancing the robustness and reliability of our IP cores, ensuring high-quality deliverables. Contributing to the development of innovative solutions that drive the Era of Smart Everything. Reducing the time-to-market for our customers by ensuring their products meet performance, power, and size requirements. Supporting the integration of more capabilities into SoCs, enabling differentiated products. Participating in a global team effort to advance cutting-edge technologies in chip design and software security. Ensuring the successful verification of complex IP cores, contributing to the overall success and reputation of Synopsys. What You ll Need: BS/BE in Electrical Engineering with 5+ years of relevant experience or MS with 3+ years of relevant experience in IP core and/or SOC verification. Proficiency in developing HVL-based test environments and implementing test plans. Hands-on experience with industry-standard simulators such as VCS, NC, and MTI, and relevant debugging tools. Strong understanding of verification methodologies like UVM/VMM/OVM. Familiarity with Verilog and scripting languages such as Perl. Basic understanding of functional and code coverage. Excellent written and oral communication skills, along with strong analytical, debugging, and problem-solving abilities. Who You Are: A self-driven individual with a passion for technology and innovation. A collaborative team player with the ability to work effectively in a global team environment. A detail-oriented professional with a commitment to delivering high-quality work. A proactive learner who stays updated with the latest industry trends and technologies.

Education: Btech/Mtech Electronics/Electrical engineering Skills/Experience: Experience in Analog Mixed-signal DDR/HBM IP layout and verification of high-speed digital layout and solid understanding of high speed signal Experience in managing the technical aspects of project execution, ensuring timely delivery maintaining high quality standards, Advanced understanding of Deep submicron effects and mitigation, Advanced tool usage, Advanced floorplanning techniques, understand digital flow, Advanced strategies, Solid understanding of CMOS and FinFET layouts and process technology in 28nm and smaller, Good understanding of ESD and latchup layout design considerations, Familiarity with ASIC physical design flow: LEF generation, Place & Route & understanding of top level verification flow, DRC/LVS, LPE, Good understanding of IO frame and pitch requirements, power rail routings, IO abutment rules and requirements, bondpad layout, EM and IR considerations, DFM, etc Scripting skills for layout automation is a plus Remote site interaction, layout co-ordination activities, ability to foster accountability and ownership through hands-on technical leadership, Excellent written and verbal communication skills in interactions with customers, and internal development teams, Responsibilities: High Speed DDR/HBM Layout design Lead the layout design, development and implement technical solutions, Provide subject matter expertise & technical leadership in High Speed design such as DDR/HBM, Work with DDR PHY team, package engineers and system engineers to meet design specs, Perform scheduling duties, Remote site interaction etc Work with local team to support critical layout and floorplanning requirements Coordination duties with other layout teams both in Bangalore and globally, to detail out layout activities and obtain layout deliverables This includes reviewing and quality checking from remote Layout teams, Strict flow adherence and policing of internal policies to secure schedules,

Supporting the existing functionality of our tools and continually enhancing their versatility, performance, and memory utilization while improving software quality. Applying extensive knowledge of algorithms and data structure design to develop robust and efficient implementations that improve tool performance and customer adoption. Interacting with other Synopsys R&D members and customers to understand their needs and product goals. Contributing to the development of complex software code-based tools in a multi-person product development environment with high dependencies and tight schedules. Exercising judgment in developing methods, techniques, and evaluation criteria to meet project goals. Collaborating with a team of enthusiastic and creative engineers to drive innovation and excellence. The Impact You Will Have: Enhancing the performance and quality of our verification tools, leading to increased customer satisfaction and adoption. Driving continuous improvement in software development processes and practices. Contributing to the development of cutting-edge technologies that power innovations in various industries. Helping Synopsys maintain its leadership position in the market by delivering high-performance solutions. Influencing the direction and success of our hardware verification tools through your expertise and innovation. Fostering a collaborative and innovative work environment that encourages growth and learning. What You ll Need: A Bachelor s degree in Electrical / Electronics / Computer-Science Engineering with a minimum of 8 years of related experience, or a Master s degree with 6 years of relevant experience. In-depth understanding of data structures, algorithms, and their applications. Excellent software development experience with C/C++ on UNIX/Linux platforms. Exposure to Python, TCL, and shell scripting languages is preferable. Exposure to HDL languages like Verilog or System Verilog is desirable, with a willingness to learn their nuances. Demonstrated history of good analytical, debugging, and problem-solving skills. Experience with complex and large software code-based tool development

The candidate would be part of the VIP group responsible for development of Verification IPs. Core responsibilities would include Designing and developing the VIP/Test-bench, Creating Verification plans, Coding sequences/Test-scenarios, Coverage driven verification. The responsibility would also include enhancement of the existing Verification IP products and interface with customers during VIP deployment. This is an opportunity to work with best-in-class verification, debug tools, Design IP & close collaboration with best protocol experts in the industry. You will work with highly professional and motivated colleagues who value and support your contribution. Requirements: Bachelors/masters with good academic record. 7+ years experience in developing HVL based verification environments, preferably using System Verilog. Exposure to coverage driven verification. Experience in verification methodologies like UVM/OVM. Exposure to complex SV test benches involving multiple protocols and VIPs. Experience in VIP development is highly desirable. Should have a strong work exposure on any of the industry standard protocols like PCIe, USB, Ethernet, MIPI etc.. Demonstrates good analysis and problem-solving skills. Have a strong passion for work and driving things to closure.

Review SerDes standards to develop analog sub-block specifications. Identify and refine circuit architectures to achieve optimal power, area, and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure the highest quality design. Oversee physical layout to minimize the effect of parasitics, device stress, and process variation. Present simulation data for peer and customer review. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. Propose solutions for post-silicon design updates. The Impact You Will Have:Drive innovation in high-speed analog integrated circuit design. Ensure optimal performance, power efficiency, and area utilization of our products. Contribute to the development of industry-leading SerDes IP. Enhance the reliability and quality of our analog sub-blocks. Support the successful integration of SerDes IP into customer products. Foster collaboration and knowledge sharing within the R&D team. Influence design strategies and best practices within the organization. What You ll Need:BE with 8+ years of relevant experience or MTech with 6+ years of relevant experience in Electrical Engineering or Computer Engineering. In-depth familiarity with transistor-level circuit design and sound CMOS design fundamentals. Detailed design experience with at least one, and familiarity with several other SerDes sub-circuits. Awareness of ESD issues and circuit techniques for addressing them. Familiarity with custom digital design and high-speed logic paths. Knowledge of design for reliability, including EM, IR, and aging considerations. Experience with tools for schematic entry, physical layout, and design verification. Hands-on experience with physical layout of high-speed circuits is a plus. Proficiency with SPICE simulators and simulation methods. Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control / data-capture. Experience with scripting languages such as TCL, Perl, C, Python, or MATLAB is desired. Who You Are:Collaborative and able to work effectively in a team environment. Detail-oriented with a strong focus on quality and reliability. Proactive problem-solver with innovative design strategies. Excellent communicator with strong documentation skills. Adaptable and able to thrive in a fast-paced, dynamic environment

Working closely with a world-class R&D team, you ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM). Working closely with customers, you will bring the detailed requirements into the factory to enable R&D for a strong, robust, and successful product development. Working closely with product development team, you will validate and end-to-end solution both internally (before shipment) as well as in customer environment. Driving the deployment and smooth execution of SLM solutions into customers projects. Enabling customers to realize the value of silicon health monitoring throughout the lifecycle of silicon bring-up, validation, through in-field operations. The Impact You Will Have: Enhancing Synopsys Silicon Lifecycle Management (SLM) IP portfolio and end-to-end solution. Driving the adoption of Synopsys SLM solutions at premier customer base worlwide. Influencing the development of next-generation SLM IPs and solutions. What You ll Need: BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field. 4+ years of hands-on experience with SoC-level functional verification or Design-for-Test (DFT) or both. Good knowledge of AXI, APB Background in verification, with at least sub-system level verification Debugging abilities to identify issues in functional verification. Knowledge of DMA, ideally should have verified a sub-system with DMA Knowledge of High-speed IO sub-systems like PCIe and USB A thorough understanding of memory mapping concepts is essential. End to end knowledge of how transactions/data flow between the HSIO interface to/from memory Knowledge and experience with Memory BIST/DFT/ATE/SLT/any other test solutions Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions Customer facing experience is a plus - educating/guiding customer on technical details of a solution Good to have: Hands-on debug experience of silicon is a plus Some programming experience to write/debug simple drivers in C Detailed knowledge of the PCIe and USB protocols Architecture/micro-architecture experience Working with FPGAs

1. At least 5 years of work experience in EDA, preferably in logic optimization and logic synthesis. 2. Strong software skills: minimum 5 years of coding experience in C++. 3. Proficiency in data structures and algorithms. 4. Strong analytical and problem-solving skills. 5. Good understanding of chip design flow. 6. Must be a team player, clear in written and oral communication skills and open to work with diverse teams across multiple time zones. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683Aschheim, GermanyEngineering Principal Analog Design EngineerMississauga, CanadaEngineering Verdi InternshipHsinchu, TaiwanInterns/Temp

What You ll Be Doing: Develop and review the verification test-plan for multi-protocol 112G PHY IP sub-system of Controller/MAC+PCS+PHY. Create and optimize the verification environment based on UVM. Verify the inter-operability of Controller/MAC, PCS, with PHY of different Tech nodes. Execute RTL simulations, Gate Level Simulations, and ensure coverage closure (Functional + Code). Deliver high-quality RTL and Simulation models to customers. Coordinate between RTL, Analog design, and Tech pub teams. Support customers with the integration and bring-up of IP in their simulation environments. Develop and deliver SV verification components for customer integration. Assist customers with silicon bring-up and debug issues when customer silicon is available. The Impact You Will Have: Ensure the delivery of robust and high-quality verification solutions for Synopsys high-performance PHY IPs. Drive innovation and efficiency in verification processes, contributing to the advancement of cutting-edge technologies. Enhance customer satisfaction through exceptional support and high-quality deliverables. Facilitate the seamless integration of Synopsys IPs into customer designs, ensuring successful product launches. Contribute to the development of industry-leading verification methodologies and best practices. Help maintain Synopsys reputation as a leader in chip design and verification solutions. What You ll Need: B.Tech/M.Tech with 7+ years of relevant experience. Proficiency in interface protocols such as Ethernet, PCIe, CXL, JESD, and CPRI. Experience with functional verification flow, Verification tools, and methodologies VMM, OVM/UVM, and System Verilog. Expertise in Gate Level Simulation with SDF, System Verilog Assertions, and coverage implementation. Fundamental knowledge of Analog and Digital mixed signal design. Proficiency in scripting and automation using TCL/Perl/Python. Excellent debug and diagnostic skills. Who You Are: You are an innovative and detail-oriented professional with a strong technical background and a collaborative mindset. Your excellent communication skills, problem-solving abilities, and interpersonal skills make you a valuable team player. You thrive in a dynamic environment, continually seeking to improve processes and deliver high-quality results. Your passion for technology and dedication to customer success drive you to excel in your role. The Team You ll Be A Part Of: You will join a dynamic and collaborative team focused on the verification of high-performance multi-protocol PHY IPs. Our team is dedicated to delivering innovative solutions and exceptional support to our customers, ensuring the successful integration and deployment of Synopsys IPs. Together, we drive technological advancements and set industry standards in chip design and verification. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

What Youll Need: BS/MS in Electrical Engineering or Computer Science with 4+ years of relevant experience, Hands-on experience with synthesis and place and route (P&R) tools, Proficiency with EDA tools such as DC, ICC2, and Fusion Compiler, Knowledge of advanced placement and routing rules, Experience with scripting languages like Perl and Tcl, Strong understanding of ASIC design flow, VLSI, and CAD development, Never give-up attitude and flexibility in supporting worldwide engagements, Who You Are: Excellent communicator with strong command of English, Highly motivated and self-driven, Detail-oriented with a focus on quality and performance, A team player who thrives in collaborative environments, Adaptable and eager to learn new technologies and methodologies,

What Youll Need: BS/MS in Electrical Engineering or Computer Science with 4+ years of relevant experience, Hands-on experience with synthesis and place and route (P&R) tools, Proficiency with EDA tools such as DC, ICC2, and Fusion Compiler, Knowledge of advanced placement and routing rules, Experience with scripting languages like Perl and Tcl, Strong understanding of ASIC design flow, VLSI, and CAD development, Never give-up attitude and flexibility in supporting worldwide engagements, Who You Are: Excellent communicator with strong command of English, Highly motivated and self-driven, Detail-oriented with a focus on quality and performance, A team player who thrives in collaborative environments, Adaptable and eager to learn new technologies and methodologies,

As an ideal candidate, you are a highly motivated and experienced Analog Design Engineer with a passion for developing state-of-the-art analog sensors You have a solid background in custom analog/mixed-signal circuit design, circuit simulations, custom layout, and post-silicon characterization You thrive in a collaborative environment, guiding junior engineers, and liaising with layout teams to achieve optimal engineering solutions Your forward-thinking approach, combined with your extensive technical knowledge, enables you to tackle the unique challenges posed by various target applications You possess a b tech or M Tech degree in Electrical Engineering with 1 years of relevant industry experience or a PhD with relevant Experience Your expertise in advanced process challenges, including ESD and reliability, and your familiarity with tools like PrimeSim, FineSim, and HSPICE, set you apart as a leader in the field What Youll Be Doing: Conceptualizing, designing, and productizing state-of-the-art on-chip Process, Voltage, Temperature, Current, and Droop sensors Developing innovative solutions in the field of on-die monitoring Liaising with the layout team to achieve the best possible engineering solutions Deploying new sensors into test chips and conducting post-silicon characterization Guiding and mentoring junior engineers and tracking their work progress Collaborating with internal teams and external customers to ensure project success The Impact You Will Have: Enhancing the performance, power, area, schedule, and yield of our products Contributing to the reliability and optimization of next-generation intelligent in-chip sensors Driving innovation in on-die monitoring solutions Improving the integration process for customers, leading to faster time-to-market Providing technical leadership and mentoring to junior engineers Ensuring the successful deployment and characterization of new sensors What You'll Need: Strong technical experience in full custom analog/mixed-signal circuit design, simulations, and custom layout Tech Knowledge of custom Analog/AMS design techniques, implementation, and verification Familiarity with advanced process challenges, including ESD and reliability Experience with tools like PrimeSim, FineSim, HSPICE, and Custom Compiler or equivalent schematic layout editor tools Who You Are: A forward-thinking and design-oriented individual A team player with excellent communication, mentoring, and interpersonal skills A problem-solver who can handle moderate scope problems and analyze several factors An established professional with practical knowledge and the ability to resolve a variety of issues Someone who can work under general supervision and achieve day-to-day objectives with moderate impact

This is a verification focused individual contributor s role. The candidate will be part of the DesignWare IP Verification R&D team at our Bangalore Design Center, India. Implement state-of-the-art Verification environments for the DesignWare family of synthesizable cores and perform Verification tasks for the IP cores. Work closely with RTL design team and be part of a global team of expert Verification Engineers. Domains will include but not be limited to USB, PCI Express, Ethernet, AMBA. Job role will have a combination of Test planning, Test environment coding both at unit level and system level, Test case coding and debugging, FC coding and analysis and meeting quality metric goals and regression management. Requirements: - BS/BE in EE with 8+ years of relevant experience or MS with 6+ years of relevant experience in the verification of IP cores and/or SOC verification. - Experience in developing HVL based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage. - HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and relevant debugging tools. - Exposure to verification methodologies such as UVM/VMM/OVM is required. - Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. - Exposure to IP design and verification processes including VIP development is an added advantage. - Basic understanding of functional & Code coverage. - It is essential that the individual has good written and oral communication skills and is able to demonstrate good analysis, debug and problem solving skills and be self-driven. Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world s broadest portfolio of silicon IP predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. At Synopsys, we re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we re powering it all with the world s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.