Review SerDes standards to develop analog sub-block specifications. Identify and refine circuit architectures to achieve optimal power, area, and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure the highest quality design. Oversee physical layout to minimize the effect of parasitics, device stress, and process variation. Present simulation data for peer and customer review. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. Propose solutions for post-silicon design updates. The Impact You Will Have:Drive innovation in high-speed analog integrated circuit design. Ensure optimal performance, power efficiency, and area utilization of our products. Contribute to the development of industry-leading SerDes IP. Enhance the reliability and quality of our analog sub-blocks. Support the successful integration of SerDes IP into customer products. Foster collaboration and knowledge sharing within the R&D team. Influence design strategies and best practices within the organization. What You ll Need:BE with 8+ years of relevant experience or MTech with 6+ years of relevant experience in Electrical Engineering or Computer Engineering. In-depth familiarity with transistor-level circuit design and sound CMOS design fundamentals. Detailed design experience with at least one, and familiarity with several other SerDes sub-circuits. Awareness of ESD issues and circuit techniques for addressing them. Familiarity with custom digital design and high-speed logic paths. Knowledge of design for reliability, including EM, IR, and aging considerations. Experience with tools for schematic entry, physical layout, and design verification. Hands-on experience with physical layout of high-speed circuits is a plus. Proficiency with SPICE simulators and simulation methods. Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control / data-capture. Experience with scripting languages such as TCL, Perl, C, Python, or MATLAB is desired. Who You Are:Collaborative and able to work effectively in a team environment. Detail-oriented with a strong focus on quality and reliability. Proactive problem-solver with innovative design strategies. Excellent communicator with strong documentation skills. Adaptable and able to thrive in a fast-paced, dynamic environment.

Responsibilities: As Senior Staff Application Engineer (AE) , you will be Working on latest Synopsys implementation technologies ( Machine Learning , Physical Synthesis , Multi Source CTS etc ) to solve complex PPA challenges faced by Synopsys customers. Working on benchmarks to displace competition implementation solutions Working with customers to develop and debug RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide appropriate solution for customers Effectively translate the findings into requirements for R&D to improve both tool behavior with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDA versions and enable customers to migrate to newer versions achieving best PPA Coming up with proactive understanding of customers pain point and come up with innovative solutions to address the same. Closely interacting with Synopsys R&D team and product development team to develop future technologies This role requires you to act as customers advocate while talking to inhouse R&D, and be a product brand ambassador while engaging with customers. Requirements: At-least 10 years of experience in Physical Implementation RTL-GDS. Experience in unsupervised debugging and resolving synth & PnR implementation challenges. Candidate must have good exposure towards methodology changes to achieve targeted PPA metrics for complex designs. Proficiency in Synopsys implementation tools is an advantage The person must be self-motivated and dedicated with solid debug skills. Requires proficiency in scripting (tcl / unix / perl). Excellent communication skills including ability to interface with customers and business unit personnel are essential.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a motivated and skilled engineer with 4 -10 years of experience in emulation solutions development You bring a strong foundation in programming concepts using C/C++ and an understanding of digital design Your expertise includes HDL languages such as System Verilog and Verilog, and you are familiar with protocols like AXI, AMBA, JTAG, AVB, CAN, and TSN You thrive in collaborative environments and have excellent communication skills Your educational background includes a b-e/ b-tech/ m-tech in Electronic & Communication or Computer Science Engineering You are passionate about developing cutting-edge emulation solutions for semiconductor customers and are eager to engage in both software development and synthesizable RTL development, What Youll Be Doing: Developing emulation solutions for industry-standard protocols such as AXI, AMBA, JTAG, AVB, CAN, and TSN, CHI, Ethernet, PCIe, CXL, UCIe CSI, DSI, DP, UFS, MMC, HDMI, DRAM, Engaging in software development using C/C++ and synthesizable RTL development using Verilog, Verifying emulation solutions to ensure they meet the highest standards of quality and performance, Interacting with customers during the deployment and debugging phases to provide technical support and ensure successful implementation, Collaborating with cross-functional teams to integrate emulation solutions with other Synopsys products and technologies, Continuously improving and optimizing emulation solutions to meet evolving industry needs and standards, The Impact You Will Have: Enhancing the efficiency and performance of semiconductor design processes through advanced emulation solutions, Contributing to the development of high-performance silicon chips and software content that drive technological innovation, Supporting semiconductor customers in overcoming design and verification challenges, leading to successful product launches, Improving the reliability and functionality of emulation solutions, thereby increasing customer satisfaction and trust in Synopsys products, Driving continuous improvement and innovation within the emulation solutions domain, Facilitating seamless integration of emulation solutions with other Synopsys technologies, enhancing overall product offerings, What Youll Need: Strong programming skills in C/C++ and understanding of OOPS concepts, Good understanding of digital design concepts, Knowledge of HDL languages such as System Verilog and Verilog, Experience with scripting languages like Perl or TCL is a plus, Understanding of ARM architecture is an added advantage, Knowledge of UVM and functional verification will be a plus, Who You Are: A team player with excellent communication skills, Detail-oriented and capable of working independently, Adaptable and eager to learn new technologies and methodologies, Proactive in identifying and solving problems, Passionate about delivering high-quality solutions, The Team Youll Be A Part Of: You will be part of a dynamic and innovative team focused on developing state-of-the-art emulation solutions for semiconductor customers The team collaborates closely with other engineering groups within Synopsys to ensure seamless integration and optimal performance of our products We value creativity, continuous learning, and a commitment to excellence, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

What You ll Need: Proficiency with STA, SDC. Proficiency with RTL, System Verilog. Strong understanding of front-end EDA design methodologies. Strong Perl, Tcl, or Python scripting skills. Prior experience with logic synthesis tools. Prior experience using or supporting SDC tools (a significant plus). Prior experience with RTL simulation and SVA (a plus). Sound communication skills, both verbal and written. Ability to produce detailed product requirement documents. BS in Electrical or Computer Engineering with 10+ years of experience in STA/Synthesis/Front-End Flows.

Developing and testing software for validation and automation purposes. Performing device-level and system-level validation and debug in post-silicon environments. Executing software tests in verification environments to ensure product quality. Working with FPGA-based setups to run validation tests and update FPGA RTL modules as needed. Creating detailed test and validation reports with statistical analysis. Interfacing with customers to capture requirements and provide post-release support. The Impact You Will Have: Contributing to the development of cutting-edge technology that drives innovation in various industries. Ensuring the reliability and performance of high-speed serial interface PHYs like USB, PCIe, and Ethernet. Enhancing the validation and debug processes through meticulous testing and analysis. Improving the overall quality and functionality of Synopsys products through rigorous validation. Supporting the continuous improvement of product development cycles. Providing valuable insights and feedback to enhance future product iterations. What You'll Need: B.Tech in ECE/CS or equivalent with 3-7 years of previous experience in a similar role/industry. Experience in programming and testing using C/C++. Board-level test and debug experience using lab equipment. Experience with embedded or resource-constrained environments. Development experience on Unix, Linux, and Windows platforms. Ability to quickly learn new workflows and adapt to new technologies. Exposure to MATLAB/Python programming is a plus. Exposure to verification and basic RTL is a plus. Excellent verbal and written communication skills.

Designing, implementing, and optimizing CI/CD pipelines for cloud and hybrid environments. Integrating AI-driven pipeline automation for self-healing deployments and predictive troubleshooting. Leveraging GitOps (ArgoCD, Flux, Tekton) for declarative infrastructure management. Implementing progressive delivery strategies (Canary, Blue-Green, Feature Flags). Containerizing applications using Docker & Kubernetes (EKS, AKS, GKE, OpenShift, or on-prem clusters). Optimizing service orchestration and networking with service meshes (Istio, Linkerd, Consul). Implementing AI-enhanced observability for containerized services using AIOps-based monitoring. Automating provisioning with Terraform, CloudFormation, Pulumi, or CDK. Supporting and optimizing distributed computing workloads, including Apache Spark, Flink, or Ray. Using GenAI-driven copilots for DevOps automation, including scripting, deployment verification, and infra recommendations. The Impact You Will Have: Enhancing the efficiency and reliability of CI/CD pipelines and deployments. Driving the adoption of AI-driven automation to reduce downtime and improve system resilience. Enabling seamless application portability across on-prem and cloud environments. Implementing advanced observability solutions to proactively detect and resolve issues. Optimizing resource allocation and job scheduling for distributed processing workloads. Contributing to the development of intelligent DevOps solutions that support both traditional and AI-driven workloads. What You ll Need: 5+ years of experience in DevOps, Cloud Engineering, or SRE. Hands-on expertise with CI/CD pipelines (Jenkins, GitHub Actions, GitLab CI, ArgoCD, Tekton, etc.). Strong experience with Kubernetes, container orchestration, and service meshes. Proficiency in Terraform, CloudFormation, Pulumi, or Infrastructure as Code (IaC) tools. Experience working in hybrid cloud environments (AWS, Azure, GCP, on-prem). Strong scripting skills in Python, Bash, or Go. Knowledge of distributed data processing frameworks (Spark, Flink, Ray, or similar)

Your expertise extends to CMOS and FinFET layouts and process technology in 28nm and below You are familiar with the layout design flow, including top-level verification flow, DRC/LVS, LPE, and have a good grasp of basic ESD and latch-up layout design considerations You understand power routes, EM and IR considerations, and DFM You have exposure to Analog/Mixed Signal circuit layout (e-g , RX, TX, PLL) Your excellent written and verbal communication skills enable you to interact effectively with internal development teams You are passionate about technology and thrive in a collaborative environment where your skills contribute to groundbreaking innovations, What Youll Be Doing: Designing and verifying complex Analog Mixed-Signal layouts, ensuring high-quality and reliable IPs, Collaborating with cross-functional teams to optimize layout designs for performance and manufacturability, Utilizing advanced tools and methodologies to mitigate deep submicron effects, Conducting floor-planning, routing, and top-level verification, Ensuring compliance with DRC, LVS, LPE standards and addressing ESD and latch-up considerations, Optimizing power routes and addressing EM and IR considerations for robust designs, The Impact You Will Have: Enhancing the performance and reliability of our high-speed SerDes IPs and other critical components, Driving innovation in Analog Mixed-Signal layout design, contributing to cutting-edge technology developments, Ensuring seamless integration and functionality of our IPs in diverse applications, Improving design efficiency and manufacturability through advanced layout techniques, Contributing to the success of our product development lifecycle by delivering high-quality designs, Supporting our mission to lead in chip design and IP integration, shaping the future of technology, What Youll Need: 6+ years of experience in Analog Mixed-Signal layout and verification, Advanced understanding of deep submicron effects and mitigation techniques, Proficiency in using advanced layout design tools and methodologies, Solid understanding of CMOS and FinFET layouts and process technology in 28nm and below, Familiarity with layout design flow, including top-level verification flow, DRC/LVS, LPE, Who You Are: You are detail-oriented, methodical, and have a deep understanding of layout design principles Your ability to communicate effectively and work collaboratively with cross-functional teams is exceptional You are proactive, always looking for innovative solutions to complex problems, and your passion for technology drives you to stay updated with the latest industry trends and advancements, The Team Youll Be A Part Of: You will be part of a dynamic and innovative team focused on developing high-performance Analog Mixed-Signal layouts Our team collaborates closely with other engineering departments to ensure the seamless integration and functionality of our IPs We value creativity, continuous learning, and a collaborative spirit to push the boundaries of technology and innovation, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Creating System verification solutions for Arm AMBA5 protocols such as CHI, AXI5/ACE5 for on-chip, chip-to-chip, die-to-die, coherent, and non-coherent design topologies. Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You ll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. In-depth understanding of cache coherency protocols such as Arm AMBA AXI/ACE, CHI; CCIX or CXL Cache. Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: Excellent problem-solving, debugging, and analytical skills. Strong programming skills and familiarity with object-oriented programming concepts. Creative and innovative mindset. Excellent verbal and written communication skills. A collaborative team player with a passion for functional verification.

Working with Synopsys customers to understand their needs and define verification scope and activities. Understanding the complexity and requirements of verification and proposing resource requirements to complete the activities. Leading a team of engineers to perform various pre-silicon verification activities on IPs/Subsystems. Anticipating problems and risks and working towards a resolution and risk mitigation plan. Assisting and mentoring the team in day-to-day activities and growing the capabilities of the verification team for future assignments. Reviewing various results and reports to provide continuous feedback to the team and improve the quality of deliverables. Reporting status to management and providing suggestions to resolve any issues that may impact execution. Collaborating with architects, designers, and pre and post-silicon verification teams to accomplish your tasks. Adhering to quality standards and good test and verification practices. Ramping up on new Verification tools and methodologies using Synopsys Products to enable customers. Working with other Synopsys teams including BU AEs and Sales to develop, broaden, and deploy Tool and IP solutions. The Impact You Will Have: Driving the success of customer projects by ensuring robust and thorough verification of SoC designs. Enhancing Synopsys reputation as a leader in verification through high-quality deliverables and customer satisfaction. Mentoring and growing the verification team, building a strong foundation for future projects. Identifying and mitigating risks early, ensuring smooth project execution and delivery. Improving verification methodologies and practices, contributing to the overall efficiency and effectiveness of the team. Collaborating with cross-functional teams to achieve seamless integration and execution of verification activities. Providing valuable feedback and insights that drive continuous improvement in verification processes and tools. What You ll Need: B.E/B. Tech/M.E/M. Tech in electronics with a minimum of 12+ years experience in SoC/IP/Subsystems verification domain. Technical expertise in various aspects of pre-silicon Verification (UVM, Coverage Analysis, Verification plan creation, debugging, etc). Good knowledge of various protocols (PCIe, Ethernet, USB, DDR, etc) and/or processor/interconnect/debug architecture. Hands-on experience with verification tools such as VCS, waveform analyzers, and third-party VIP integration (such as Synopsys VIPs). Ability to lead a team to perform verification on complex SoC/IP/Subsystems. Experience with planning and managing verification activities for SoC/Subsystems/IPs. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills.

What You will Be Doing: Supporting the People team s digital transformation initiatives. Building and maintaining People tools, ensuring they meet organizational needs. Collaborating with various stakeholders to gather requirements and implement solutions. Providing expert guidance with Employee Central to optimize functionality that includes but not limited to position management, foundation management, workflows, notifications and permissions. Managing support tickets to ensure prompt resolution. Processing uploads and maintaining process documentation and/or playbooks. Collaborating with HR and IT teams to ensure seamless integration of People systems with existing or new enterprise applications. Evaluating and implementing AI-driven solutions to enhance HR functions Conducting regular system audits and troubleshooting issues as they arise. Training and supporting end-users to ensure they are proficient in using People tools. The Impact You Will Have: Enhancing the efficiency and effectiveness of HR processes through optimized People tools. Contributing to the successful implementation of digital transformation projects within the People team. Improving Employee and Manager experiences through systems. Ensuring data integrity and accuracy within our People systems. Facilitating better decision-making through improved data accessibility and reporting capabilities. Reducing system downtime by proactively identifying and resolving issues. Empowering team members with the knowledge and tools they need to succeed. What You Will Need: 2+ years configuration experience with People systems like SuccessFactors or similar core HR systems. Strong analytical and problem-solving skills. Excellent communication skills, both written and verbal. Experience in supporting digital transformation initiatives. Ability to conduct system audits and troubleshoot data or system issues. Demonstrated track record of strong problem-solving skills and organizational skills.

Academic Qualification/Skills required: B.E / M.E. in Electronic & Communication / Computer Science Engineering High performance individual to work on Synopsys next generation emulation solutions for PCIe, USB, Ethernet protocols Good knowledge of one of peripheral protocols primarily PCIe, USB, Ethernet Knowledge of System Level verification and validation, and digital design concepts Knowledge of languages such as Verilog, System Verilog, C/C++, and scripting languages- Perl/TCL/Shell, Python Knowledge of emulation and prototyping domains an added advantage 6-8 Years of experience in protocols/design verification and validation, scripting, and automation Good communication skills and team player At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683 Aschheim, Germany Engineering Principal Analog Design Engineer Mississauga, Canada Engineering Verdi Internship Hsinchu, Taiwan Interns/Temp

Your exceptional debugging skills and proficiency in software and scripting languages such as Perl, Tcl, and Python set you apart With a keen eye for detail, you maintain high standards of product quality and excel in communication and leadership roles You thrive in collaborative environments, working closely with cross-functional teams to develop and execute comprehensive validation plans Your analytical mindset allows you to perform in-depth root cause analysis and proactively address potential issues, ensuring the readiness of products for customer deployment You are an experienced professional with a b-tech or m-tech degree and a minimum of 6-8 years of related experience, ready to make a significant impact on our Formality tool, What Youll Be Doing: Execute and lead product validation of Synopsys's Formality tool by understanding requirements specifications, functional specifications, and customer use cases Lead a team of 5 or more product validation engineers Collaborate with cross-functional teams such as R&D, Product Engineering to develop, implement, and execute comprehensive validation plans based on our technical roadmap and specifications Define and manage scope, schedule, and risks associated with the validation objectives Perform in-depth customer incoming root cause analysis to understand the product weak areas and hot spots and execute proactive testing to improving product quality Use product expertise to provide technical recommendations, identify, diagnose and troubleshoot issues, and propose solutions to ensure quality and readiness of the product/solution for customer deployment Analyze product validation data to identify trends, discrepancies, and areas for improvement Prepare detailed validation reports for presenting to multi-functional teams and management The Impact You Will Have: Ensuring the quality and reliability of Synopsys's Formality product to keep standing out as a leading LEC solution in the industry Enabling timely and successful deployment of high-performance designs for our customers Contributing to the innovation and advancement of LEC and product validation technologies Strengthening collaboration and communication across R&D, Product Engineering, and Field teams What Youll Need: Tech or equivalent and a minimum of 8 years of related experience or M Self-motivated individual with deep domain knowledge in Logic Equivalence Checking (LEC) including expertise in debugging and resolving LEC failures using Synopsyss Formality tool Experience and sound knowledge in design implementation including datapath optimization, CTS, UPF and DFT instrumentation Sound knowledge in HDL including SystemVerilog and VHDL Exceptional debugging skills Proficiency in software and scripting skills (Perl, Tcl, Python) Experience in cross-functional teamwork, driving projects and mentoring Who You Are: Details oriented with a focus on maintaining high standards of product quality Excellent communication, organizational, risk assessment/mitigation, and time management skills Ability to abstract up and communicate meaningful conclusions and define next steps Excellent communication and leadership skills The Team Youll Be A Part Of: You will be part of a dedicated product validation team for Formality, working closely with R&D, product engineering and field applications engineering teams Your team focuses on ensuring the high quality of new releases and features of Formality tool, enabling customers to accurately and timely validate their high-performance designs Together, you will tackle complex technical challenges and drive continuous improvement in our product validation processes, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process, Inclusion and Diversity are important to us Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability,

What You ll Need: 8 to 15 years of relevant industry experience with team leading experience. Advanced knowledge of high-performance cores/IPs implementation methodologies. Experience with Synopsys implementation tools such as RTLA and Fusion Compiler. Proficiency in developing PPA methodologies for complex IPs. Strong understanding of the latest technology nodes and their applications. Proven track record of leading and managing engineering teams.

What You ll Need: Bachelor s or masters degree in electrical engineering or a related field. Exceptional knowledge of layout design ideas and methodologies. Proficiency in industry-standard layout tools such as Synopsys Custom Compiler or Cadence Virtuoso. Excellent problem-solving and debugging skills. Ability to work effectively in a team environment. Good communication and interpersonal skills. Who You Are: Detail-oriented with a strong focus on precision and quality. Adaptable and eager to learn new techniques and technologies. Collaborative team player with a positive attitude. Self-motivated and able to work independently when required. Committed to continuous improvement and innovation.

What You ll Be Doing: Developing and writing user documentation for various Digital and Mixed Signal IPs. Planning, organizing, and editing technical specifications, engineering schematics, application notes, and user guides. Interfacing with the Design Engineering team to collect raw content and transform it into user-friendly documentation. Ensuring strict adherence to style guides and documentation processes. Collaborating with other teams to produce high-quality customer documentation. Contributing to the documentation roadmap and having a significant impact on all customer documentation produced. The Impact You Will Have: Enhancing the usability and accessibility of technical documentation for various IP product lines. Improving customer satisfaction by providing clear and concise user guides and application notes. Streamlining the documentation process and ensuring adherence to style guides. Facilitating better communication between design engineers and end-users through well-crafted documentation. Contributing to the overall success of Synopsys products by providing essential support materials. Driving innovation in documentation practices and setting new standards for technical writing. What You ll Need: Degree or masters in electronics, science, hardware, computing, software, physics, mathematics, or engineering discipline. 3-7 years of technical writing experience in the software or hardware industry. Excellent problem-solving skills and strong logical reasoning. Experience with authoring tools such as FrameMaker. Excellent English writing and speaking skills.

What You'll Need: Project Management Experience: 2+ years of experience specifically in technical program management with overall experience of 8 to 12 years, Hands-on working knowledge in Python / Perl Ability to do code reviews and take part in design discussions, Product Security Knowledge: Strong understanding of product security principles, especially related to open-source projects, Experience with cloud platforms such as AWS, Azure, or Google Cloud, Communication skills: Excellent verbal and written communication abilities for cross-functional collaboration, Stakeholder Management: Ability to define project objectives and collaborate closely with stakeholders, Project Planning: Skills in developing and maintaining comprehensive project plans,

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a highly skilled and motivated Physical Design Engineer with a passion for innovation and a proven track record in the semiconductor industry You thrive in dynamic environments and are adept at managing multiple projects simultaneously Your deep understanding of the full design cycle from RTL to GDSII, particularly in advanced FinFET nodes, positions you as a technical driver in your field You possess excellent communication skills, enabling you to effectively collaborate with cross-functional teams and stakeholders Your solid software and scripting skills, combined with your expertise in CAD automation methods, make you an invaluable asset to any project You are autonomous, capable of making timely judgments, and able to handle interruptions with ease, What Youll Be Doing: Driving the physical implementation of high-speed interface IPs and test-chips from SYN to GDS, Utilizing your software and scripting skills to enhance CAD automation methodology for the team Collaborating with multiple functional groups, including front-end, analog and CAD teams, Focusing on advanced SerDes developments, including the latest 112G/224G PAM4 standards, Leading the physical design team to ensure on-time delivery of projects, The Impact You Will Have: Contributing to the successful delivery of high-performance silicon IPs that power the Era of Smart Everything, Ensuring the integration of more capabilities into SoCs, meeting unique performance, power, and size requirements, Reducing the risk and time-to-market for differentiated products, Driving technological innovation through advanced SerDes development, Enhancing Synopsys reputation as a leader in chip design and verification, Supporting the company's mission to power the worlds most advanced technologies for chip design and software security, What Youll Need: 10+ years of physical design experience with recent contributions to project tape-outs or IP delivery Strong tcl scripting skills in Place & Route Tools (Fusion Compiler / ICC2 / Others) Understand version control & have experience in one of the version control software (Perforce / Git / Svn / Clearcase) Experience with advanced FinFET nodes, TSMC 7 nanometer or below, Solid understanding of IC design, implementation flows, and methodologies for deep submicron design, Proven track record for technical steering of physical design teams for on-time delivery, Who You Are: Excellent communicator with the ability to engage with peer groups and customers, Autonomous and capable of making timely judgments, Proficient in software and scripting skills (Perl, Tcl, Python), Knowledgeable in CAD automation methods and industry standards in deep sub-micron designs, Able to travel internationally as required, The Team Youll Be A Part Of: You will be part of a collaborative team within the Mixed-Signal IP organization, working closely with front-end, analog, and CAD teams The team focuses on the physical implementation of complex mixed-signal IPs and test-chips across multiple process technologies, with a specific emphasis on advanced high-speed SerDes platforms, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

What You ll Need: MSEE or BSEE with 10+ years of digital design and verification experience. Strong understanding of verification methodologies like System Verilog and UVM. Familiarity with RTL coding and design principles. Proficiency in scripting languages like Perl and Python for automation. Excellent debugging and troubleshooting abilities. Experience with test chip and full chip knowledge is an advantage. Proven leadership and team-building skills.

Develop and maintain circuit design methodology flows and documentation. Identify and refine circuit implementations to achieve optimal power, area and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure highest quality design. Oversee physical layout to minimize the effect of parasitic, device stress, and process variation. Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits. Present simulation data for peer and customer review. Mentor and Review the progress of junior engineers. Document design features and test plans. Required Qualifications: Bachelor with 2 years experience or MSEE (or PhD) in Electrical Engineering, Computer Engineering, or similar technical field In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals. Silicon-proven experience implementing circuits like bandgap references, voltage regulators. Detailed design experience with high custom logic design Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects. Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.). Experience with EDA tools for schematic entry, physical layout, and design verification. High proficiency with spice simulators including HSPICE, Finesim and XA Knowledgeable in Verilog-A and/or System-Verilog for analog behavioral modeling and simulation-control / data-capture. Plus Qualifications: Ability to provide automationfor rapid and dynamic design needs is highly sought-after Experience with STA and cell characterization such as Nanotime, Primetime, SiliconSmart Experienced in STAR or similar extractor to debug extraction issues Extensive programming skills in languages such as Python, Perl, TCL and C/C++

Specifications Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and Simulation tools Lint, CDC, Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background Experience with high speed design greater than 600MHz and with P&R aware synthesis including usage of tools such as Fusion Compiler is a significant plus Experience with Perforce or similar revision control environment Knowledge of Perl/Shell scripts Exposure to quality processes in the context of IP design and verification is an added advantage Ability to work/ Prior experience as a Technical Lead for a small team is a major plus Should be able to mentor and technically lead a team of designers In addition, the candidate should have good communication skills, should be a team player and possess good problem solving skills and show high levels of initiative