Specify, design, and implement advanced verification environments for synthesizable IP cores Conduct rigorous verification tasks to ensure IP cores meet Synopsys high-quality standards Collaborate with RTL designers and global verification teams to deliver robust solutions Work on next-gen AMBA and serial protocols for commercial, enterprise, and automotive applications Engage in unit/system-level test planning, test environment development, test case creation/debugging, and functional coverage analysis Manage regression suites and ensure quality metrics are consistently met The Impact You Will Have: Enhance the performance and reliability of Synopsys IP cores across diverse industries Contribute to innovation in verification methodologies, improving overall process efficiency Help ensure timely delivery of high-quality IPs aligned with evolving customer and market needs Play a vital role in advancing technologies used in commercial, enterprise, and automotive applications Collaborate with global teams and drive consistency across verification standards Influence best practices in IP verification through your contributions and leadership What You'll Need: BSEE with 5+ years or MSEE with 4+ years of relevant experience Proficient in SystemVerilog for testbench development and verification planning Strong HVL programming skills and familiarity with simulation and debugging tools Experience with verification methodologies such as VMM, OVM, or UVM Knowledge of industry protocols including AMBA, PCIe, USB, DDR, MIPI-I3C/UFS/Unipro, and Ethernet

Create comprehensive test plans and verification strategies aligned with specifications Develop modular and reusable testbenches using SystemVerilog Write both directed and random tests to validate functionality Perform functional and code coverage modeling, analysis, and reviews Debug mismatches between RTL design and C-model behavior Integrate internal and third-party verification IP for full-chip simulations Review and optimize existing test suites and verification environments Mentor junior engineers and assist in skill development Ensure test plans are fully traceable to design specifications using coverage databases The Impact You Will Have: Lead innovation in processor and IP verification strategies Strengthen IP quality through rigorous and structured verification practices Enhance verification efficiency through test automation and coverage closure Contribute to the success of Synopsys industry-leading silicon IP Help standardize and refine verification flows and methodologies Foster a culture of mentorship and continuous improvement within the team What You'll Need: Bachelor's degree in Engineering (preferably from a reputed institution) 36 years of experience in hardware verification Experience in microprocessor or processor-based system verification is a strong plus Proficient in SystemVerilog, Verilog, and UVM/OVM methodologies Skilled in C programming, assembly language, Perl scripting, and makefiles Familiarity with advanced verification techniques such as formal methods, low-power, and functional safety is advantageous

Lead and contribute to digital design of high-speed serial interface PHY IPs (USBx, PCIex, Ethernet, Display, HDMI) Define and enhance micro-architecture based on customer, analog, system, or interface layer requirements Implement RTL in Verilog, ensuring code quality with tools like Spyglass (Lint, CDC, RDC) Collaborate with verification teams to validate functionality and handle edge/corner cases Develop timing constraints and drive synthesis, DFT insertion, and timing closure with physical design teams Own blocks from specification through delivery with strong micro-architecture and RTL skills The Impact You Will Have: Enhance performance and robustness of PHY IPs powering next-gen electronics Deliver innovative and high-quality digital designs that meet evolving industry needs Influence technology development at the intersection of digital and mixed-signal design Enable efficient collaboration across design, verification, and physical teams Support customer success with reliable and optimized IP solutions Strengthen Synopsys leadership in semiconductor IP through excellence in digital design What You'll Need: 58 years of ASIC digital design experience Strong expertise in Verilog RTL and micro-architecture design Hands-on experience with timing constraints and synthesis flows Proficiency with Spyglass (Lint, CDC, RDC) or equivalent tools Scripting experience in TCL, PERL, or Python Strong debugging, analysis, and detail orientation

What You'll Be Doing: * Designing and developing DDR I/O circuits to meet performance and power specifications. * Collaborating with cross-functional teams to integrate analog circuitry into SoCs. * Executing circuit design tasks with a focus on product quality and efficiency. * Conducting layout reviews and ensuring adherence to design methodologies. * Participating in design reviews and providing technical insights. * Staying updated with the latest advancements in CMOS processes and deep submicron technologies. The Impact You Will Have: * Enhancing the performance and efficiency of our silicon IP portfolio. * Contributing to the rapid integration of advanced capabilities into SoCs. * Reducing the time-to-market and risk for our customers products. * Driving innovation in analog design and setting new industry standards. * Strengthening Synopsys position as a leader in chip design and verification. * Empowering the development of high-performance, differentiated products. What You'll Need: * BTech/MTech in Electrical Engineering or a related field. * 4+ years of experience in CMOS circuit design and layout methodology. * Strong knowledge of deep submicron process technologies. * Familiarity with ASIC design flow and JEDEC standards for DDR interfaces. * Excellent written and verbal communication skills. Who You Are: * A collaborative team player with a proactive approach. * Detail-oriented with a commitment to quality and efficiency. * Innovative and adaptable, always seeking to learn and grow. * Effective communicator, able to convey technical information clearly.

The Impact You Will Have: Enhance layout design methodologies and best practices, contributing to the overall quality and efficiency of the design process. Improve project forecasting capabilities by leveraging advanced monitoring and scheduling techniques. Boost productivity across ASIC design cycles through the development and automation of internal tools. Ensure design integrity and manufacturability through meticulous physical verification and design rule checks. Stay at the forefront of industry advancements, bringing the latest trends and technologies into Synopsys design practices. Collaborate effectively with cross-functional teams, driving innovation and continuous improvement in design methodologies. What You'll Need: Bachelor's or master's degree in engineering or a related field. 2 to 3+ years of experience in A&MS frontend and backend views & collaterals development flows. Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Excellent problem-solving and systematic skills. Ability to work effectively in a team-oriented environment. Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV). Good communication and interpersonal skills.

What You'll Be Doing: Design and development of transistor-level analog and mixed signal layout. Creating device/block level floorplans, performing placement, routing, and physical verification. Troubleshooting physical verification issues to achieve clean and desired results. Creating and reviewing layout documents to ensure they meet quality standards and are delivered on time. Collaborating with cross-functional teams to optimize the layout design process. Staying updated with the latest industry trends and advancements in layout design techniques. The Impact You Will Have: Contributing to the development of high-performance silicon chips. Ensuring the reliability and accuracy of analog and mixed signal layouts. Enhancing the efficiency of the layout design process. Supporting the delivery of high-quality products that meet industry standards. Facilitating innovation and continuous improvement in layout design techniques. Helping Synopsys maintain its leadership position in the semiconductor industry. What You'll Need: Bachelor's or master's degree in a relevant field. Minimum 3 years of experience in analog and mixed signal circuit layout. Experience with analog layout flow and EDA tools for custom mixed signal layout flows. In-depth knowledge of semiconductor device physics and analog circuits. Proficiency in CMOS and FINFET technologies and CMOS fabrication technology. Understanding of deep sub-micron effects and their impact on layout. Knowledge of EMIR, cross talk, shielding, and their impact on design. Experience in Tcl is a plus.

Develop emulation solutions for standard protocols including AXI, AMBA, JTAG, AVB, CAN, and TSN Implement software using C/C++ and synthesizable RTL in Verilog Verify emulation platforms to ensure high performance and robust quality Provide technical support to customers during deployment and debug phases Collaborate with other teams to integrate emulation components into broader Synopsys offerings Continuously enhance and optimize emulation solutions to meet evolving protocol and industry standards The Impact You Will Have: Improve semiconductor development processes through high-performance emulation Enable faster and more reliable silicon chip verification for various customer use cases Support global semiconductor leaders with robust deployment and troubleshooting assistance Enhance the stability and integration of Synopsys emulation products Foster innovation and continuous improvement in emulation technology offerings Strengthen Synopsys product ecosystem and customer trust through top-tier engineering support What You'll Need: 37 years of experience in emulation, verification, or related development Strong programming skills in C/C++ with OOPS knowledge Proficiency in HDL languages like Verilog and System Verilog Good understanding of digital design and emulation concepts Experience with scripting languages such as Perl or TCL (preferred) Exposure to ARM architecture, UVM methodology, and functional verification is a plus

What You'll Be Doing: Ensure analog sub-block performance adheres to SerDes standards and architecture document specifications. Identify and refine circuit implementations to achieve optimal power, area, and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure highest quality design. Oversee physical layout to minimize the effect of parasitic, device stress, and process variation. Present simulation data for peer review. Ownership of analog and mixed-signal building block that is integrated as part of a larger SerDes design. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. The Impact You Will Have: Contribute to the development of cutting-edge SerDes technologies that drive high-performance computing and communication systems. Enhance the overall performance and efficiency of our analog and mixed-signal designs, ensuring they meet industry standards. Improve the quality and reliability of our designs through meticulous verification and layout oversight. Support the seamless integration of analog and mixed-signal building blocks within larger SerDes designs. Drive innovation by identifying and implementing optimal circuit solutions for complex design challenges. Collaborate with cross-functional teams to deliver high-quality IP products that meet customer requirements. What You'll Need: BTech or MS with 2+ years of SerDes/High-Speed analog design experience. Familiarity with transistor-level circuit design of fundamental analog and mixed-signal building blocks. Sound CMOS design fundamentals. Design experience with some of the following SerDes sub-circuits: equalizers, data samplers, voltage/current-mode drivers, serializers, LDOs, Bandgap, ADC/DAC, PLLs, DLLs. Who You Are: Detail-oriented and meticulous in your approach to design and verification. A strong communicator, able to present complex technical data clearly and concisely. Collaborative and team-oriented, thriving in a peer-review environment. Innovative and solution-focused, always seeking to optimize design performance. Proactive and self-motivated, with a passion for continuous learning and improvement.

Own and develop UVM-based testbench environments for IP/SoC verification Design verification architecture, testplans, and SVA based on protocol specifications (PCIe, CXL, UCIe, AXI, etc.) Drive all aspects of the verification lifecycle including testbench creation, coverage closure, and debugging Collaborate with RTL design teams to resolve issues and close functional coverage Conduct peer reviews to maintain high testbench code quality Contribute technical papers and patent ideas on testbench innovations and verification methodologies Work closely with global teams and ensure timely project execution The Impact You Will Have: Deliver reliable and robust verification solutions that ensure high-quality IP/SoC design Influence UVM testbench architecture through innovation and best practices Improve efficiency and accuracy in verification through SVA and advanced debugging Enable faster time-to-market by streamlining simulation and debug processes Contribute to Synopsys IP leadership by ensuring verification excellence across global projects What You'll Need: 48 years of experience in UVM-based verification for IP/SoC Strong SystemVerilog knowledge and protocol understanding (PCIe, CXL, UCIe, AXI, etc.) Hands-on experience with functional coverage closure and SystemVerilog Assertions (SVA) Proficiency in simulation tools and waveform debug tools like DVE/Verdi Familiarity with version control tools (e.g., Perforce) Scripting knowledge (Python, TCL) is an added advantage Strong communication, problem-solving skills, and ability to work across teams and geographies

What You'll Be Doing: Analyze various analog circuit techniques for dynamic and static power reduction, performance enhancement, and area reduction. Develop Analog Full custom circuit macros, including Transmitters, Receivers, Clocking circuits, equalizers, serializers, de-serializers, and Analog Front End needed for High-Speed PHY IP. Leverage your understanding of circuit design and layout, along with knowledge of bipolar, CMOS, passive structure, and interconnect failure modes. Collaborate with experienced teams locally and globally to deliver high-performance silicon chips. Create simulation environments to verify circuit specifications and debug circuits as needed. Optimize layouts and parasitics to enhance circuit performance and reliability. The Impact You Will Have: Contribute to the design and verification of advanced silicon chips, accelerating their development and manufacturing processes. Enable customers to optimize their chips for power, cost, and performance, significantly reducing project schedules. Drive innovations in high-speed physical interfaces, enhancing the performance and reliability of our products. Collaborate with global teams to leverage diverse expertise and deliver cutting-edge technology solutions. Influence the development of next-generation processes and models for manufacturing high-performance silicon chips. Ensure the successful implementation of analog and mixed-signal circuit designs in advanced CMOS technologies. What You'll Need: BE with 5+ years of relevant experience or MTech with 4+ years of relevant experience in Electrical/Electronics/VLSI Engineering or a related field. Strong fundamentals in CMOS circuit design, device physics, and sub-micron design methodologies. Experience with analog transistor-level circuit design in nanometer technologies. Familiarity with Multi Gbps range high-speed designs, including PAM4 serdes architectures. Proficiency in creating simulation environments and debugging circuits. Who You Are: Detail-oriented with excellent problem-solving skills. Strong communicator, capable of collaborating with teams across different locations. Innovative thinker with a passion for technology and circuit design. Proactive and self-motivated, with the ability to work independently and as part of a team. Adaptable and open to learning new techniques and methodologies.

Lead and contribute to digital design of high-speed serial interface PHY IPs (USBx, PCIex, Ethernet, Display, HDMI) Define and enhance micro-architecture based on customer, analog, system, or interface layer requirements Implement RTL in Verilog, ensuring code quality with tools like Spyglass (Lint, CDC, RDC) Collaborate with verification teams to validate functionality and handle edge/corner cases Develop timing constraints and drive synthesis, DFT insertion, and timing closure with physical design teams Own blocks from specification through delivery with strong micro-architecture and RTL skills The Impact You Will Have: Enhance performance and robustness of PHY IPs powering next-gen electronics Deliver innovative and high-quality digital designs that meet evolving industry needs Influence technology development at the intersection of digital and mixed-signal design Enable efficient collaboration across design, verification, and physical teams Support customer success with reliable and optimized IP solutions Strengthen Synopsys leadership in semiconductor IP through excellence in digital design What You'll Need: 58 years of ASIC digital design experience Strong expertise in Verilog RTL and micro-architecture design Hands-on experience with timing constraints and synthesis flows Proficiency with Spyglass (Lint, CDC, RDC) or equivalent tools Scripting experience in TCL, PERL, or Python Strong debugging, analysis, and detail orientation

Ensure timely order acceptance and maintain an accurate order backlog Review and interpret customer contracts to ensure compliance with internal policies Provide guidance on complex or non-standard order setups in SAP Collaborate with internal teams including Revenue Accounting, Sales, Credit, Distribution, and IT Participate in corporate projects and initiatives, offering input and recommendations Support quarter/year-end close activities including workload coordination and issue resolution Propose and implement improvements in order management procedures and documentation Act as a backup for supervisor/manager during peak workload periods The Impact You Will Have: Ensure accurate and timely order processing to meet customer and company expectations Enhance order management efficiency through process improvements and standardization Drive coordination among multiple internal departments to streamline operations Support the organization's ability to scale by handling complex order scenarios Contribute to strategic initiatives that improve internal controls and operational effectiveness Strengthen team capabilities during critical financial periods by taking leadership roles What You'll Need: 35 years of relevant experience in order management or related functions Strong hands-on expertise with SAP systems and Microsoft Excel Experience in reviewing contracts and applying order acceptance policies Bachelor's degree or equivalent professional experience Ability to collaborate effectively across departments and recommend process enhancements Familiarity with corporate compliance and financial reporting procedures is a plus

You will contribute to the continued development of ourgraphical user interface that helps our customers setup calculations usingdensity functional theory, semi-empericalmodelsor force field potentials. The tasks require extensive experience withscientific computing,simulationsofquantumsystems anda proven interest in UI development.We are looking for a talented individual with: Personal experience with quantum codes Strong general background in solid state physicsor chemistry General programming skills, in particular Python and C++ Proven interest inlayouting, visual design and UI programming Excellent written and oral communication skills in English The successful applicant Is an outstanding individual with strong competences in programming or atomic-scale modelling Has a broad set of skills and is ready to apply them to whatever task assigned Is dedicated with focus on getting the job done without sacrificing quality Has 6+ years of experience in related field Is a team player Enjoys communicating and helping other people Has a positive mindset and is motivated by challenging projects Is self-motivated and takes responsibility and initiative Synopsys offers you A challenging and dynamic work environment A role in cutting-edge technology development Highly competent and motivated team members To be part of a company with a strong growth and a high potential To see a direct impact of your work

Category Engineering Hire Type Employee Job ID 10118 Remote Eligible No Date Posted 18/03/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: We are seeking a highly skilled Senior DevOps Engineer who is proactive and knowledgeable with a passion for cutting-edge technologies for the central software engineering organization at Synopsys. As an ideal candidate, you are experienced in driving engineering efforts related to Continuous Integration and Delivery (CI/CD), automated testing, and deployment across all phases of the Software Development Life Cycle. You are adept at implementing frameworks and best practices for deploying automation via pipelines into various environments including on-premises, cloud (AWS, GCP, Azure), and containerized environments (Kubernetes, Docker Swarm). Your expertise lies in building platforms and frameworks that enable consistent, verifiable, and automated management of applications and infrastructure. You thrive in an Agile framework, identifying, creating, designing, and integrating processes for repeatable, automated software delivery. You are an advocate for innovation and automation, always seeking ways to enhance efficiency and effectiveness in CI/CD processes. Your strong communication skills enable you to effectively design cross-functional deployments and triage efforts, and you possess excellent analytical and problem-solving abilities. Additionally, you are skilled in mentoring and providing oversight to other DevOps team members, guiding them in implementing recommended solutions for process automation and best practices. What You'll Be Doing: Driving engineering efforts related to Continuous Integration and Delivery (CI/CD) and automated testing and deployment across all phases of the Software Development Life Cycle. Implementing frameworks and best practices for deploying automation via pipelines into on-premises, cloud environments (AWS, GCP, Azure), and containerized environments (Kubernetes, Docker Swarm). Building platforms and frameworks to create consistent, verifiable, and automatic management of applications and infrastructure in both on-premises and cloud infrastructure. Defining the development pipeline to ensure that software development flows match operational testing and deployment goals. Working within the Agile framework to identify, create, design, and integrate processes for repeatable, automated software delivery. Identifying and initiating the development of metrics and dashboards to monitor the adoption and maturity of DevOps practices. Advocating for innovation and automation, continuously seeking ways to improve CI/CD processes. Reviewing technical operations and providing mentoring and oversight to other DevOps team members in implementing recommended solutions for process automation and best practices. The Impact You Will Have: Enhancing the efficiency and effectiveness of our CI/CD pipelines to ensure high-quality software delivery. Enabling consistent and automated management of applications and infrastructure, improving reliability and scalability. Streamlining the software development lifecycle, ensuring alignment with operational testing and deployment goals. Driving the adoption and maturity of DevOps practices through the development of metrics and dashboards. Fostering a culture of innovation and automation within the engineering team. Mentoring and guiding other DevOps team members, enhancing their skills and knowledge. What You'll Need: Bachelor's or Master's degree in Engineering streams such as Computer Science, EEE, ECE, IT, or equivalent. At least 5 years of overall software development/deployment/infra experience. Cloud and other architect-level industry certifications (AWS, GCP, Azure, Security, etc.). 3-5 years of DevOps experience in modern tech stack to support products in the cloud. 2+ years of scripting/automation experience with Bash, Python, Perl, and/or other scripting languages. Strong CI/CD experience with code build, source control, testing, continuous integration, and delivery using standard DevOps CI/CD tools (Jenkins, Git). 3+ years of experience with containerization, source control (Docker/Docker Hub/Helm), and container orchestration (Kubernetes, Docker Swarm). Familiarity with programming languages (C/C++/Java). Familiarity with build tools (Make, CMake, Maven, Gradle) and dependency management (Conan). Experience developing Ansible Playbooks/Jenkins automation for infrastructure automation. Proficiency in multiple DevOps-related tools and technologies (JIRA, Confluence, GitHub/Azure, Jenkins, Ansible, Prometheus, Grafana, ELK). Who You Are: A proactive and knowledgeable engineer with a passion for cutting-edge technologies. An advocate for innovation and automation, always seeking ways to enhance efficiency and effectiveness in CI/CD processes. A strong communicator, able to effectively design cross-functional deployments and triage efforts. An excellent problem solver with strong analytical skills. A mentor and guide, capable of providing oversight and guidance to other DevOps team members. The Team You'll Be A Part Of: You will be part of a dynamic and innovative central software engineering organization at Synopsys. The team is focused on driving engineering efforts and automating processes to deliver high-quality EDA products. We work collaboratively within an Agile framework, continuously seeking ways to improve and innovate in the field of DevOps.

Execute and lead product validation of Synopsys's Formality tool by understanding requirements specifications, functional specifications, and customer use cases Lead a team of 5 or more product validation engineers Collaborate with cross-functional teams such as R&D, Product Engineering to develop, implement, and execute comprehensive validation plans based on our technical roadmap and specifications Define and manage scope, schedule, and risks associated with the validation objectives Perform in-depth customer incoming root cause analysis to understand the product weak areas and hot spots and execute proactive testing to improving product quality Use product expertise to provide technical recommendations, identify, diagnose and troubleshoot issues, and propose solutions to ensure quality and readiness of the product/solution for customer deployment Analyze product validation data to identify trends, discrepancies, and areas for improvement Prepare detailed validation reports for presenting to multi-functional teams and management The Impact You Will Have: Ensuring the quality and reliability of Synopsys's Formality product to keep standing out as a leading LEC solution in the industry Enabling timely and successful deployment of high-performance designs for our customers Contributing to the innovation and advancement of LEC and product validation technologies Strengthening collaboration and communication across R&D, Product Engineering, and Field teams What You'll Need: B.Tech or equivalent and a minimum of 5 years of related experience or M.Tech or equivalent and a minimum of 3 years of related experience Self-motivated individual with deep domain knowledge in Logic Equivalence Checking (LEC) including expertise in debugging and resolving LEC failures using Synopsys's Formality tool Experience and sound knowledge in design implementation including datapath optimization, CTS, UPF and DFT instrumentation Sound knowledge in HDL including SystemVerilog and VHDL Exceptional debugging skills Proficiency in software and scripting skills (Perl, Tcl, Python) Experience in cross-functional teamwork, driving projects and mentoring Who You Are : Details oriented with a focus on maintaining high standards of product quality Excellent communication, organizational, risk assessment/mitigation, and time management skills Ability to abstract up and communicate meaningful conclusions and define next steps Excellent communication and leadership skills

Lead and execute Analog Mixed-Signal layout design for high-speed DDR/HBM IPs Deliver robust and high-quality physical layout designs ensuring adherence to DDR/HBM specs Apply deep understanding of FinFET and CMOS technology at 28nm and below Handle high-speed digital layout verification with attention to signal integrity Implement advanced floorplanning techniques and apply submicron mitigation strategies Coordinate with remote layout teams globally for layout quality and deliverables Drive internal flow adherence for tape-out readiness and schedule compliance Collaborate with PHY designers, package engineers, and system teams to meet design objectives Oversee IO layout requirements including bondpads, ESD, IR/EM, and DFM considerations Utilize physical verification tools and support Place & Route and top-level verification flows The Impact You Will Have: Shape next-gen high-speed memory interface solutions through expert physical design Ensure quality layout execution in advanced nodes, directly impacting performance and reliability Drive project delivery across global teams with technical leadership and coordination Enable Synopsys to meet customer demand in high-speed memory IPs with quality and timeliness Reinforce design flow adherence and process discipline to ensure tape-out success Contribute to the robustness of global layout practices through review and mentorship What You'll Need: 612 years of experience in Analog Mixed-Signal layout, specifically with DDR/HBM IPs Expertise in FinFET and CMOS layout at 28nm and below Strong knowledge of signal integrity, DRC/LVS/LPE, ESD/latchup, and IO pitch/layout constraints Familiarity with ASIC physical design flows including LEF, Place & Route, and verification Hands-on experience with advanced layout tools and scripting (Perl, TCL, etc. preferred) Proven leadership in global coordination and layout delivery Excellent communication and customer interaction skills

What You'll Be Doing: Develop CMOS embedded memories such as SP SRAM, DP SRAM, Register File, and ROM. Design architecture and circuit implementation, focusing on ultra high speed, ultra low power, or high density designs. Perform schematic entry, circuit simulation, layout planning, layout supervision, design verification, and validation. Interface with CAD and Frontend engineers for memory compiler automation, EDA model generation, and full verification flow. Perform bit cell development and verification, and drive physical layout design and verification. Provide support and/or perform other duties as assigned and required. The Impact You Will Have: Contribute to the development of high-performance silicon chips and software content. Enhance the efficiency and performance of our CMOS memory designs. Drive innovation in ultra high speed, ultra low power, and high density memory designs. Ensure the highest quality in bit cell development and physical layout design. Collaborate effectively with CAD and Frontend engineers to streamline automation and verification processes. Support the continuous improvement and advancement of our memory design technology. What You'll Need: Bachelor's or Master's degree in Electrical Engineering, Telecommunication, or related fields. Proficiency in CMOS memory design, circuit simulation, memory layout designs, layout parasitic extraction, and layout verification tools and debugging techniques. Programming capability in C-Shell and Perl; knowledge of C++ or Java script is a plus. Strong analytical and problem-solving skills with attention to detail. Experience in developing documents, reports, or presentations for a range of tasks. Who You Are: Self-motivated, self-directed, detail-oriented, and well-organized. Possess excellent analytical, problem-solving, and negotiation skills. Capable of leading and mentoring trainees and junior engineers, as well as managing projects. Strong command of English, both verbal and written. Exhibit strong interpersonal communication and teamwork skills. Professional, critical/logical thinker, and focused on future goals. Highly committed to continuous learning and professional development.

What You'll Be Doing As a security-focused project manager, you will: Manage security-related projects, ensuring alignment with organizational goals and industry standards. Oversee security initiatives in open-source environments, including vulnerability assessment, remediation coordination, and promoting best practices within engineering teams. Collaborate with stakeholders to define project objectives, scope, and deliverables. Develop and maintain comprehensive project plans. Facilitate effective communication and collaboration across cross-functional teams. Monitor program progress and implement solutions to keep projects on track. Drive continuous improvement by evaluating current processes and recommending enhancements for efficiency and security effectiveness. Identify challenge areas and risks requiring executive engagement. Address issues and roadblocks, escalating with appropriate detail and priority. Lead problem resolution through fact-based, conscious, and high-quality decision-making. The Impact You Will Have By leading product security initiatives, you will: Ensure the security and integrity of Synopsys products, particularly in open-source environments. Develop strategic project plans aligned with organizational goals and industry standards. Enhance cross-functional collaboration for improved communication and project outcomes. Implement solutions to maintain project timelines and high-quality delivery. Promote best practices and continuous security improvements within engineering teams. Identify and mitigate risks through proactive management. Leverage data analytics to provide valuable insights and recommendations for product security enhancements. Foster a culture of security awareness and compliance within the organization. Contribute to the overall success of Synopsys security and data engineering initiatives. What You'll Need To be successful in this role, you should have: Project Management Experience: At least 2+ years in technical program management, with an overall experience of 812 years. Programming Skills: Hands-on knowledge of Python and Perl, with the ability to review code and participate in design discussions. Product Security Expertise: Strong understanding of product security principles, particularly in open-source environments. Cloud Platform Experience: Familiarity with AWS, Azure, or Google Cloud. Communication Skills: Excellent verbal and written communication for cross-functional collaboration. Stakeholder Management: Ability to define project objectives and engage effectively with stakeholders. Project Planning Skills: Proficiency in developing and maintaining comprehensive project plans.