What You'll Be Doing: Perform daily customer collections activities to maximize timely collections and minimize uncollectible adjustments. Negotiate repayment plans with delinquent customers. Continuously reconcile customer and GL accounts. Provide standard and ad-hoc reporting to management, such as monthly A/R aging reports and related summaries, risk analysis, and assist with quarterly audit reports. Forecast cash collections and analyze historic payment trends. Perform credit analysis of new and existing customers daily. Approve and recommend credit limits appropriate to the risk profile through diligent risk assessment and monitoring. Highlight significant credit risk and collection issues to senior management. Review contractual payment terms and approve or make recommendations. Coordinate with internal partners including Sales, Finance, Tax, OM, and Legal. Automate systems and processes, update internal policies, procedures, and controls where necessary. The Impact You Will Have: Ensure timely collection of payments, positively impacting the company's cash flow. Mitigate financial risks by conducting thorough credit analyses and monitoring customer accounts. Enhance the accuracy and reliability of financial reporting through diligent reconciliation and analysis. Support strategic decision-making with comprehensive risk assessments and financial forecasts. Foster strong relationships with customers, improving overall satisfaction and retention. Drive process improvements, contributing to the efficiency and effectiveness of the finance function. What You'll Need: Proficiency in SAP, particularly the FSCM Collections Module is a plus. Advanced Microsoft Excel skills. Proven track record of driving process efficiencies. Bachelor's degree in finance or a related field (optional). M&A experience is a plus.

What You'll Be Doing: Designing, developing, and updating training materials including presentations, videos, and other support content. Creating clear and concise technical documentation that effectively communicates complex engineering concepts. Collaborating with subject matter experts (SMEs) and other stakeholders to ensure the accuracy and relevance of training content. Managing multiple projects simultaneously, ensuring timely delivery of high-quality training content. Reviewing training materials to ensure they meet quality standards and are effective in achieving learning objectives. Gathering feedback to continuously improve training content and delivery methods. Maintaining the Knowledge Base site (SharePoint) to keep the training content accessible and up to date. The Impact You Will Have: Enhancing the skills and knowledge of engineering teams through high-quality training content. Ensuring the effective communication of complex technical concepts to diverse audiences. Supporting the continuous improvement of training materials based on feedback and evolving needs. Contributing to the overall success of product engineering initiatives by providing accurate and relevant training resources. Facilitating the adoption and usability of Synopsys products and solutions through well-designed training programs. Maintaining an up-to-date and accessible Knowledge Base for ongoing learning and development. What You'll Need: Proficiency in presentation creation tools (e.g., PowerPoint) and enterprise content management systems (e.g., SharePoint). Strong understanding of electronic engineering principles and practices across various disciplines. Excellent written and verbal communication skills with the ability to simplify complex technical information. Ability to create and edit multimedia content including presentations, charts, graphics, videos, voiceovers, and animations. Strong organizational and project management skills, with the ability to manage multiple priorities effectively.

Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. Solving complex problems and debugging issues effectively. Executing layout floorplanning, routing, and physical verifications to meet stringent quality requirements. Ensuring compliance with DRC, LVS, ERC, and antenna rules. Applying deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies (7nm and below). Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. The Impact You Will Have: Enhancing the performance and reliability of Synopsys DDR/HBM/UCIe IPs. Accelerating the integration of advanced capabilities into SoCs. Reducing risk and improving time-to-market for differentiated products. Driving innovation in semiconductor technology and design. Contributing to the success of Synopsys Silicon IP business. Fostering a collaborative and inclusive work environment. What You'll Need: BTech/MTech degree in a relevant field. 4+ years of experience in analog layout design. Proven track record in developing high-quality layouts and meeting verification timelines. Strong understanding of deep submicron effects and floorplan techniques. Exposure to layout matching, ESD, latch-up, EMIR, DFM, and LEF generation.

Designing, coding, and testing software components with proficiency in C++ programming. Creating and maintaining Makefiles, BOM files, and build systems to streamline the software build and deployment process. Utilizing scripting languages such as Python, Shell, and Perl for automation, testing, and system-level tasks. Applying ML/AI technologies to enhance operations projects and develop sophisticated algorithms. Collaborating with cross-functional teams throughout the software development lifecycle, from concept to deployment. Troubleshooting and resolving software-related issues in a Linux environment. The Impact You Will Have: Contributing to the development and enhancement of cutting-edge software applications. Improving the efficiency and reliability of software build and deployment processes. Automating repetitive tasks and optimizing system-level operations. Enhancing the capabilities of operations projects with advanced ML/AI technologies. Ensuring seamless collaboration and communication within cross-functional teams. Resolving complex software issues and contributing to a robust and reliable software environment. What You'll Need: Bachelor's or Master's degree in Computer Science, Software Engineering, or a related field. 26 years of relevant experience in software development and R&D projects. Strong proficiency in C++ programming and software design. Experience with data structures and algorithms. Knowledge of version control systems (Perforce, Git, SVN). Familiarity with Makefiles and build systems. Proficiency in scripting languages like Python, Shell, and Perl. ML/AI experience is essential. Solid understanding of Linux environments.

What You'll Be Doing: Designing test plans and processes for SaaS applications, including end-to-end flow and service layer testing on both Cloud and on-prem platforms. Analyzing architecture, user flows, and corner cases to define automation requirements, ensuring correct-by-construction code. Designing automation test suites for Microservices, API, and UI functions. Writing comprehensive test plans and defining test metrics. Implementing test scripts with measurable test coverage. Compiling and publishing reports of coverage and quality metrics. The Impact You Will Have: Ensuring the delivery of high-quality software products that meet user needs and expectations. Enhancing the reliability and performance of our SaaS applications through rigorous testing. Contributing to the continuous improvement of our testing processes and methodologies. Supporting the development team by identifying and resolving defects early in the development cycle. Improving customer satisfaction by ensuring that our products are robust and reliable. Driving innovation in our testing practices and staying ahead of industry trends. What You'll Need: Experience in writing automation scripts using Python, PowerShell, and Terraform. Experience in setting up CI/CD pipelines using Jenkins and Azure DevOps. Experience with REST API testing and UI automation tools like Selenium. Strong knowledge of Nest Node JS, Containers, Kubernetes ecosystem, and Azure Services. Experience with test frameworks such as Jest, Postman, Protractor, and Selenium. Who You Are: A strong analytical thinker with excellent problem-solving skills. An effective communicator who can convey complex technical concepts to various stakeholders. A proactive team player who thrives in a collaborative environment. A detail-oriented individual who is committed to delivering high-quality work. Adaptable and open to learning new technologies and methodologies.

What You'll Be Doing: Building the data engineering and analytics infrastructure for our new Enterprise Data Platform using Snowflake and Fivetran. Leading the development of data models, algorithms, data pipelines, and insights to enable data-driven decision-making. Collaborating with team members to shape the design and direction of the data platform. Working end-to-end on data products, from problem understanding to developing data pipelines, dimensional data models, and visualizations. Providing support and advice to business users, including data preparation for predictive and prescriptive modeling. Ensuring consistency of processes and championing best practices in data management. Evaluating and recommending new data tools or processes. Designing, developing, and deploying scalable AI/Generative AI and machine learning models as needed. Providing day-to-day production support to internal business unit customers, implementing enhancements and resolving defects. Maintaining awareness of emerging trends in AI, Generative AI, and machine learning to enhance existing systems and develop innovative solutions. The Impact You Will Have: Driving the development of a cutting-edge data platform that supports enterprise-wide data initiatives. Enabling data-driven decision-making across the organization through robust data models and insights. Enhancing the efficiency and effectiveness of data management processes. Supporting business users in leveraging data for predictive and prescriptive analytics. Innovating and integrating advanced AI and machine learning solutions to solve complex business challenges. Contributing to the overall success of Synopsys by ensuring high-quality data infrastructure and analytics capabilities. What You'll Need: BS with 5+ years of relevant experience or MS with 3+ years of relevant experience in Computer Sciences, Mathematics, Engineering, or MIS. 5 years of experience in DW/BI development, reporting, and analytics roles, working with business and key stakeholders. Advanced knowledge of Data Warehousing, SQL, ETL/ELT, dimensional modeling, and databases (e.g., mySQL, Postgres, HANA). Hands-on experience with modern data stack tools, including cloud data warehouses (Snowflake), transformation tools (dbt), and cloud providers (Azure, AWS). Experience with data ingestion tools (e.g., Fivetran, HVR, Airbyte), CI/CD (GitLab, Kubernetes, Airflow), and data catalog tools (e.g., Datahub, Atlan) is a plus. Proficiency in scripting languages like Python, Unix, SQL, Scala, and Java for data extraction and exploration. Experience with visualization tools like Tableau and PowerBI is a plus. Knowledge of machine learning frameworks and libraries (e.g., Pandas, NumPy, TensorFlow, PyTorch) and LLM models is a plus. Understanding of data governance, data integrity, and data quality best practices. Experience with agile development methodologies and change control processes.

Designing and developing DDR I/O circuits to meet stringent performance and power requirements. Collaborating with cross-functional teams to integrate silicon IP into SoCs efficiently. Conducting detailed circuit simulations and layout verification to ensure design accuracy. Interfacing with internal teams to address design issues and implement solutions. Maintaining up-to-date knowledge of industry standards and technological advancements. Documenting design processes and methodologies for future reference and continuous improvement. The Impact You Will Have: Driving the development of high-performance silicon IP that powers next-generation technologies. Enhancing the capability and efficiency of SoCs, enabling faster time-to-market for differentiated products. Contributing to the innovation and advancement of technologies in the Era of Smart Everything. Ensuring high-quality design outputs that meet industry standards and customer expectations. Collaborating with a team of experts to push the boundaries of what's possible in chip design. Playing a key role in the success of Synopsys Silicon IP business by delivering reliable and cutting-edge solutions. What You'll Need: BTech/MTech in Electrical Engineering or related field. Minimum of 3 years of experience with MTech or 5 years with BTech in CMOS circuit design and layout methodology. Strong knowledge of deep submicron process technologies and CMOS processes. Familiarity with JEDEC requirements for DDR interfaces and standards. Experience with ASIC design flow and ESD concepts is an advantage.

You will contribute to the continued development of ourgraphical user interface that helps our customers setup calculations usingdensity functional theory, semi-empericalmodelsor force field potentials. The tasks require extensive experience withscientific computing,simulationsofquantumsystems anda proven interest in UI development.We are looking for a talented individual with: Personal experience with quantum codes Strong general background in solid state physicsor chemistry General programming skills, in particular Python and C++ Proven interest inlayouting, visual design and UI programming Excellent written and oral communication skills in English The successful applicant Is an outstanding individual with strong competences in programming or atomic-scale modelling Has a broad set of skills and is ready to apply them to whatever task assigned Is dedicated with focus on getting the job done without sacrificing quality Has 6+ years of experience in related field Is a team player Enjoys communicating and helping other people Has a positive mindset and is motivated by challenging projects Is self-motivated and takes responsibility and initiative Synopsys offers you A challenging and dynamic work environment A role in cutting-edge technology development Highly competent and motivated team members To be part of a company with a strong growth and a high potential To see a direct impact of your work

You will contribute to the continued development of ourgraphical user interface that helps our customers setup calculations usingdensity functional theory, semi-empericalmodelsor force field potentials. The tasks require extensive experience withscientific computing,simulationsofquantumsystems anda proven interest in UI development.We are looking for a talented individual with: Personal experience with quantum codes Strong general background in solid state physicsor chemistry General programming skills, in particular Python and C++ Proven interest inlayouting, visual design and UI programming Excellent written and oral communication skills in English The successful applicant Is an outstanding individual with strong competences in programming or atomic-scale modelling Has a broad set of skills and is ready to apply them to whatever task assigned Is dedicated with focus on getting the job done without sacrificing quality Has 6+ years of experience in related field Is a team player Enjoys communicating and helping other people Has a positive mindset and is motivated by challenging projects Is self-motivated and takes responsibility and initiative Synopsys offers you A challenging and dynamic work environment A role in cutting-edge technology development Highly competent and motivated team members To be part of a company with a strong growth and a high potential To see a direct impact of your work

Contribute to modeling, integration, and testing of various peripherals in SystemC-based platform modeling framework Understand IP modeling requirements and generate ESL model specifications Resolve technical issues related to IP modeling and platform integration Guide junior engineers and consultants on SoC platform creation and validation Support software bring-up and debug platform integration issues Collaborate with cross-functional teams to ensure successful execution and delivery The Impact You Will Have: Advance platform modeling and integration of high-performance silicon chips Improve efficiency and scalability of SystemC-based frameworks across domains like Automotive and Wireless Ensure accurate and functional SoC platform creation and validation Provide mentorship and technical leadership to junior engineers Deliver high-quality modeling solutions that align with Synopsys innovation goals Enable successful deployment of next-gen technologies through robust platform models What You'll Need: Bachelor's or Master's in Electrical Engineering or Computer Science 6+ years of industry experience Strong proficiency in C++, SystemC/TLM modeling Solid understanding of bus/memory architectures and SoC interfaces Familiarity with protocols such as IEEE 802.3 Ethernet, PCIe (preferred) Experience in modeling SoC peripherals using C++/SystemC/HDL (preferred) Knowledge of AMBA, AXI, OCP, or NoC protocols (preferred) Exposure to assembly or high-level application development and multicore platforms (preferred)

Strong desire to learn and explore new technologies. Demonstrates good analysis and problem-solving skills. Prior knowledge and experience in tools like DC, ICC2, PT-SI, FC is a definite advantage. Should be a strong team player, excellent communicator as the role involves daily technical interaction with local, US counterparts. What You'll Be Doing: He/She will be part of SNPS DDR/HBM/Ucie IP implementation team and responsible for the implementation and integration of world class DDRs at the cutting-edge technology nodes. Timing closure above 4GHz, mixed signal hard macro IP integration, building efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job. Prior working knowledge in the DDR/HBM/HBI timing closure, implementation would be an added advantage. Should be very hands-on and able to technically lead a team of 4-6 junior engineers towards successful completion of project on-time and with top quality. Who You Are: Typically requires a minimum of 6+ years of related experience after post-graduation. Possesses a full understanding of specialization area plus working knowledge of multiple related areas. A team player who independently resolves a wide range of issues in creative ways on a regular basis. Customarily exercises independent judgment in selecting methods and techniques to obtain solutions. Performs in project leadership role. Contributes to complex aspects of a project. Determines and develops approach to solutions. Work is independent and collaborative in nature. Provides regular updates to manager on project status. Represents the organization on business unit and/or company-wide projects. Guides more junior peers with aspects of their job.

Category Engineering Hire Type Employee Job ID 10209 Remote Eligible No Date Posted 30/03/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and initiative-taking individual with a strong technical background inPhysicaldesign,physicalverificationand STA at IP/block/full chip level implementation/methodology. You thrive in collaborative environments andpossessa passion for creating innovative technology. Yourexpertiselies in working with advancedFinfet and GAA process challenges, and you have a proactive analytical approach with a keen eye for detail. Your dedication to delivering high-quality results is complemented by excellent communication and people skills, allowing you to effectively collaborate with both internal teams and external customers. Driven by a desire to innovate, you are eager to contribute to the success of ourcutting-edgetechnology products. WhatYou'llBe Doing: * Conceptualizing, designing, and productizingstate-of-the-artRTLto GDS implementationfor SLM monitors realized through ASIC design flow. * Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics. * DevelopingDigital BE activities includessynthesis, pre-layout STA,SDCconstraints development, floor planning, bump placement, power planning, MV design techniques,VCLP, UPFunderstanding,placement, CTS, routingand collaborating with thedifferent functionalteamsto achieveoptimaldesign solutions. *Post layout STA,timing& functionalECOdevelopment, timingsignoffmethodologyat higher frequency IPdesignsclosure. * Physical verification, DRC, LVS, PERC, ERC, Antenna, EMIR, Power signoff. * Creating new flows/methodologies and updating existing ones through collaboration with architects and circuit design engineering teams. * Pre-layout and post-layout timing closure and timing model characterizations across various design corners to ensure reliability and aging requirements for Automotive & consumer products. The Impact You Will Have: * Accelerating the integration of next-generation intelligent in-chip sensors and analytics into technology products. *Optimizingperformance, power, area, schedule, and yield of semiconductor lifecycle stages. * Enhancing the reliability and differentiation of products in the market with reduced risk. * Driving innovation inPhysical design, physical verification, STA and signoffdesign methodologies and tools. * Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. * Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. WhatYou'llNeed: * BS/B.Techor MS/M.Techdegree in Electrical Engineering with 5+ years of relevant industry experience. * StrongPhysical design, physical verification,pre&post layoutSTA andEMIR/Powersignoffexperience, includingSDCdevelopment, UPF/Mutlivoltagedesigndevelopment experience. * Experience in DRC, LVS, DFM cleaning andtimingclosureis mandatory. * Proficiency with Digital design tool from any EDA vendor, preferably from Synopsys tools like FC/VCLP/PT/PT-PX/ICV and Redhawk * Sound understanding of Physical design, Physical verification and STA and signoff concepts. * Experience with design methodologies like developing custom scripts and enhancing flows for better execution. Experience in scripting with TCL/PERL is required. Who You Are: * Proactive and detail-oriented with excellent problem-solving skills. * Adept at working independently and providingphysical design and signoffsolutions. * Excellent communicator and team player, capable of collaborating effectively with diverse teams. * Innovative thinker with a passion for technology and continuous improvement. * Committed to delivering high-quality results and achieving project goals. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Will be working on the next generation High Performance designs for commercial, Enterprise and Automotive applications Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create architecture and micro-architecture with detailed design documents for some of the components of the design for medium to high complexity functionality Be an individual contributor in the Design Tasks - RTL coding of design, synthesis, CDC analysis, debug, Test development etc. May need to interact with customers to discuss/ understand customers specification requirements, if needed The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide Must have Bachelors/Masters degree in EE/EC/VLSI with 5+ years of relevant experience in the following areas: Hands-on design of data path designs and algorithmic blocks such as Reed Solomon FEC encoder and Decoder as per IEEE 802.3-bj, ck, bs specifications, BCH codes, Parallel CRC computation architectures, MAC SEC engines. Experience in datapath architecture designs for area, latency, throughput trade-offs Knowledge of one or more of protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro/ SD-MMC/ USB/AMBA (AMBA2, AXI) Experience with control path-oriented designs like asynchronous FIFO, DMA architectures, SPRAM/ DPRAM interface design, etc. Hands-on experience with architecting/ micro-architecture/ detailed design from Functional Specifications Hands-on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and Simulation tools Lint, CDC, Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background Experience with high speed design greater than 600MHz and with P&R aware synthesis including usage of tools such as Fusion Compiler is a significant plus Experience with Perforce or similar revision control environment Knowledge of Perl/Shell scripts Exposure to quality processes in the context of IP design and verification is an added advantage Ability to work/ Prior experience as a Technical Lead for a small team is a major plus Should be able to mentor and technically lead a team of designers

As part of the team, design, develop and drive improvements to the verification technology Support the existing functionality and continually aim to enhance the versatility, performance and memory utilization while improving quality of the software. Work requires algorithm, data structure design as well as developing robust and efficient implementations. Interact with other members of Synopsys R&D, customer as necessary to understand customer needs and product goals. Skills Required: A minimum of 8 years of related experience. Excellent Software development experience with C / C++ on UNIX/Linux platforms Broad understanding of data structures, algorithms and their applications. Should have experience working in a multi-person product development environment with high dependencies and tight schedules. It is essential that the applicant is highly motivated and has solid desire to learn and explore new technologies. Demonstrated history of good analytical, debugging and problem-solving skills. Experience with complex software tool development and usage with legacy code base Exercise of judgment in developing methods, techniques, and evaluation criteria to meet project goals. Ability to work in both self-directed and collaborative settings. Understanding/Experience in Unified Power Format (UPF) would be beneficial Good written and oral communication skills, for team collaboration and product presentations. Preferred Skills: Special consideration given to those with background and experience in formal verification and/or synthesis techniques. Experience in Compilers and RTL Synthesis would be beneficial Knowledge of software specification and design process, and regression testing. Ability to know about customer wants and needs in the formal verification user community, by working with sales and field personnel.

Review SerDes standards to define analog sub-block specifications Architect and refine circuits for optimal power, area, and performance Propose and implement verification strategies using advanced simulator features Supervise physical layout to manage parasitics, stress, and process variations Present simulation results to peers and customers for validation Document design methodologies, test plans, and circuit features Provide electrical characterization guidance and suggest post-silicon updates The Impact You Will Have: Innovate in high-speed analog IC design for next-gen SerDes IP Ensure efficient, reliable analog designs meeting stringent specs Influence architectural strategies and best practices in analog design Enable successful integration of analog blocks into customer systems Strengthen the R&D team through knowledge sharing and technical leadership Drive product performance and power efficiency across SerDes solutions What You'll Need: BE with 8+ years or MTech with 6+ years of experience in Electrical/Computer Engineering Strong expertise in transistor-level CMOS analog design Design experience with one or more SerDes sub-circuits (e.g., PLL, RX, TX) Awareness of ESD design strategies and reliability (EM, IR, aging) Familiarity with custom digital logic and high-speed paths Proficiency in SPICE simulation, schematic/layout tools, and design verification Experience with Verilog-A modeling and scripting (TCL, Perl, Python, MATLAB)

Review SerDes standards to develop analog sub-block design specifications Define and refine circuit architectures to meet power, area, and performance goals Devise design and verification strategies leveraging advanced simulation tools Supervise physical layout to manage parasitics, device stress, and variability Present simulation data for internal and customer-facing reviews Document design methodologies, features, and test strategies Support electrical characterization and propose post-silicon design updates The Impact You Will Have: Drive innovation in high-speed analog circuit design for SerDes IP Ensure optimal trade-offs in power, area, and performance Enhance reliability and manufacturability of analog sub-blocks Support successful integration of SerDes IP into customer solutions Contribute to best practices in analog design and simulation within the team Influence product development strategies with expert design knowledge What You'll Need: BE with 8+ years or MTech with 6+ years of relevant experience in Electrical/Computer Engineering Strong expertise in transistor-level CMOS circuit design and analog design fundamentals Experience in designing SerDes sub-circuits like PLLs, TX, RX, CDR, etc. Understanding of ESD protection, custom digital design, and high-speed logic Familiarity with reliability concerns such as EM, IR drop, and aging Proficient with schematic/layout tools and SPICE-based simulators Knowledge of Verilog-A for behavioral modeling and scripting in TCL, Perl, Python, or MATLAB

What You'll Be Doing: Design and development of transistor-level analog and mixed signal layout. Creating device/block level floorplans, performing placement, routing, and physical verification. Troubleshooting physical verification issues to achieve clean and desired results. Creating and reviewing layout documents to ensure they meet quality standards and are delivered on time. Collaborating with cross-functional teams to optimize the layout design process. Staying updated with the latest industry trends and advancements in layout design techniques. The Impact You Will Have: Contributing to the development of high-performance silicon chips. Ensuring the reliability and accuracy of analog and mixed signal layouts. Enhancing the efficiency of the layout design process. Supporting the delivery of high-quality products that meet industry standards. Facilitating innovation and continuous improvement in layout design techniques. Helping Synopsys maintain its leadership position in the semiconductor industry. What You'll Need: Bachelor's or master's degree in a relevant field. Minimum 3 years of experience in analog and mixed signal circuit layout. Experience with analog layout flow and EDA tools for custom mixed signal layout flows. In-depth knowledge of semiconductor device physics and analog circuits. Proficiency in CMOS and FINFET technologies and CMOS fabrication technology. Understanding of deep sub-micron effects and their impact on layout. Knowledge of EMIR, cross talk, shielding, and their impact on design. Experience in Tcl is a plus.

What You'll Be Doing: Designing and implementing SOC solutions for various applications, ensuring high performance and reliability. Collaborating with cross-functional teams to define and develop SOC architecture and specifications. Conducting verification and validation of SOC designs to ensure compliance with industry standards and customer requirements. Optimizing SOC designs for power, performance, and area (PPA) to meet project objectives. Debugging and resolving issues in SOC designs, utilizing advanced tools and methodologies. Providing technical guidance and mentorship to junior engineers, fostering a culture of continuous improvement and innovation. Job Description and Requirements The role is for RTL Design and Signoff of IP/Subsystem/SoC Design in the System Solutions Group (SSG). At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, methodology to enable our customers complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. As part of this role, you can expect to develop and deliver your expertise in RTL Signoff and RTL Design Techniques while working on activities such as Lint/CDC/RDC Checks, Timing Constraints Development, Preliminary Synthesis, Formality and RTL Design. The role will expose you to various innovative technologies deployed for RTL Quality Signoff for Semiconductors. Responsibilities Perform RTL Quality Signoff Checks such as LINT, CDC, RDC. Understand the design/architecture and develop timing constraints for synthesis and timing. Run preliminary synthesis to ensure that the design can be synthesized as intended. Run formality to ensure equivalence of RTL and gates. Integrate IPs in SoCs/Subsystems and create RTL design as per need of the customer. Required B.E/B. Tech/M.E/M. Tech in electronics with 4-9 years experience in RTL Design and Verification. Hands-on experience on static verification tools such as Spyglass performing LINT, CDC, RDC. Good conceptual understanding of design/architecture pitfalls across clock/reset domain crossing. Good conceptual understanding of RTL rule checks. Hands-on experience on synthesis and timing constraints development. Candidates with experience on ARM based technologies (Coresight Debug, Processor architecture, etc.) will be preferred.

What You'll Be Doing: Discovering, designing, and implementing changes to existing IT infrastructure to improve reliability, performance, and standardization. Collaborating with engineering and business units to translate customer, business, and technical requirements into SRE practices and enhancements. Ensuring efficient resource utilization and continuously improving processes through automation and internal tools. Troubleshooting production issues, providing root cause analysis, and designing solutions to prevent future occurrences. Monitoring services and creating intelligent alarming for quicker incident detection and resolution. Maintaining vulnerability management processes and policies using a risk-based priority methodology. Collaborating with various teams and platform owners on all vulnerability management and reporting. Applying architectural and infrastructure disciplines to solve business problems strategically. Participating in off-hours maintenance activities and being part of the on-call rotation schedule. The Impact You Will Have: Enhancing the reliability and performance of Synopsys IT infrastructure. Driving significant productivity, robustness, agility, and time-to-market advantages in the creation of Synopsys products and solutions. Leading corporate infrastructure transformation and IT operations leadership. Implementing automation and internal tools to improve service delivery, maturity, and scalability. Reducing production issues through effective troubleshooting and root cause analysis. Ensuring proactive monitoring and quicker incident detection and resolution. What You'll Need: Extensive experience with infrastructure technologies such as Linux, Windows, cloud computing, virtualization, and containerization. Deep understanding of IT infrastructure services and their dependencies. Experience with administration, security hardening, and performance tuning of Linux and Windows OS. Experience with developing service level indicators and objectives, and building alerts. Proficiency in ITIL processes and frameworks. Hands-on experience with infra-automation tools like GitHub, Jenkins, Terraform, and Ansible. Experience with one or more programming languages such as Java, Python, Go, or NodeJS.

Bridge and close gaps between Emulation hyper scaler designs, IP, and product validation Drive requirements for Emulation deployment and integration into customer verification strategies Report on key metrics and implement continuous improvements in Emulation PE and R&D Stay current with evolving interface standards and specification errata (e.g., PCIe, DDR) Guide the correct usage and enhancement of Emulation IP for digital design validation Foster deep collaboration between Emulation IP and Design IP teams for alignment and quality The Impact You Will Have: Strengthen cross-functional collaboration, improving overall product quality and customer satisfaction Shift industry perspectives and internal strategies for using Emulation in design and verification Define innovative requirements that shape future product development in Emulation Integrate best-in-class methodologies and standardize workflows across teams Influence the direction of digital design architecture validation using Emulation technologies What You'll Need: 8+ years of experience in Emulation, hardware verification, or related domains Strong exposure to large design emulation compiles and advanced protocols like PCIe and DDR Hands-on experience with Zebu or similar emulation platforms Proven track record in emulation-driven product deployment Excellent collaboration and communication skills to drive alignment across global teams Comfortable navigating matrixed, international environments and leading change initiatives