Job description (VC Spyglass Lint Technology on VC Platform) Responsible for designing, developing, troubleshooting the core VC-Static engine, which is integral part of Lint Design and develop Lint standard and customized Lint checks using VC Platform technologies for analysis, synthesis and simulations. Will be working closely with other teams both locally and globally Design and development of state of the art EDA tools involving development in one or more of the following areas-: developing new and innovative algorithms in the area of electronic design automation. Skills Required 4 to 10 years of Software development experience Familiarity with ASIC design flow and the EDA tools and methodologies used therein. Fluent in C++ with work experience in data-structures and algorithms. Excellent algorithm analysis skills and a good knowledge of data structures. Good knowledge of Tcl and Perl-based development on Unix. Good knowledge of Verilog, SystemVerilog & VHDL HDL. Ability to develop new architecture Knowledge on GenAI is Value added Self-motivation, self- discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success Quality focus one who believes in quality and wants to make a difference Experience of production code development on Unix/Linux platforms. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Develop emulation solutions for protocols such as AXI, PCIe, CXL, UCIe, Ethernet, HDMI, DRAM, and more Write and maintain C/C++ software and synthesizable RTL using Verilog Verify emulation solutions for performance, reliability, and standard compliance Interact with customers for deployment, debug, and technical support Work with cross-functional teams to integrate emulation into broader Synopsys platforms Optimize and enhance emulation solutions for emerging protocol requirements and design complexity The Impact You Will Have: Boost semiconductor design productivity through reliable emulation platforms Drive success of high-performance chip designs through timely emulation support Enhance customer trust and product reliability through quality support and integration Contribute to the innovation of next-gen emulation frameworks at Synopsys Ensure compatibility and excellence across industry protocols Support rapid prototyping and verification for customers worldwide What You'll Need: Strong programming skills in C/C++ with a solid grasp of OOPS Proficient in digital design and HDL languages like Verilog/System Verilog Scripting experience (Perl, TCL) preferred Understanding of protocol standards and ARM architecture is a plus Exposure to UVM/functional verification is desirable Good analytical, debugging, and collaboration skills

Collaborate with a cross-functional, multi-disciplinary team to identify new methodological approaches to layout analysis and define algorithmic solutions Develop software modules and shared libraries throughout a product life cycle, from prototype to customer release Implement testing and benchmarking automation for Pattern Analytics tools Coordinate the creation of engineering-level technical documentation for the supported products Troubleshoot and solve customer problems after deployment Stay updated with the latest advancements in EDA, data science, and machine learning to continuously enhance product offerings The Impact You Will Have: Drive innovations in semiconductor design and silicon manufacturing flows through advanced pattern analytics Enhance the efficiency and accuracy of layout analysis methodologies, contributing to the overall improvement of EDA tools Facilitate the development of cutting-edge computational solutions that address critical gaps in current industrial solutions Ensure the successful deployment and adoption of new EDA products by providing robust technical documentation and customer support Contribute to the continuous evolution of Synopsys product offerings, maintaining our leadership in the industry Empower semiconductor companies and software developers with innovative tools that streamline design and verification processes What You'll Need: Ph.D. or B.Tech/M.Tech in Electrical Engineering (EE), Computer Science (CS), or related fields, with a minimum of 5 years of industry experience Expertise in Python programming with a strong focus on data structures, advanced proficiency in libraries such as NumPy, Pandas, Matplotlib, Scipy, and development of new Python APIs or commands Extensive experience in C++ and/or Java Practical experience in developing Machine Learning models, including Graph Neural Network (GNN) models and LLM's type of models Knowledge in probability and statistics, Electronic Design Automation (EDA), VLSI Physical Design Verification, and/or Mask Data Generation

Execute and lead product validation of Synopsys's Formality tool by understanding requirements specifications, functional specifications, and customer use cases Lead a team of 5 or more product validation engineers Collaborate with cross-functional teams such as R&D, Product Engineering to develop, implement, and execute comprehensive validation plans based on our technical roadmap and specifications Define and manage scope, schedule, and risks associated with the validation objectives Perform in-depth customer incoming root cause analysis to understand the product weak areas and hot spots and execute proactive testing to improving product quality Use product expertise to provide technical recommendations, identify, diagnose and troubleshoot issues, and propose solutions to ensure quality and readiness of the product/solution for customer deployment Analyze product validation data to identify trends, discrepancies, and areas for improvement Prepare detailed validation reports for presenting to multi-functional teams and management The Impact You Will Have: Ensuring the quality and reliability of Synopsys's Formality product to keep standing out as a leading LEC solution in the industry Enabling timely and successful deployment of high-performance designs for our customers Contributing to the innovation and advancement of LEC and product validation technologies Strengthening collaboration and communication across R&D, Product Engineering, and Field teams What You'll Need: B.Tech or equivalent and a minimum of 5 years of related experience or M.Tech or equivalent and a minimum of 3 years of related experience Self-motivated individual with deep domain knowledge in Logic Equivalence Checking (LEC) including expertise in debugging and resolving LEC failures using Synopsys's Formality tool Experience and sound knowledge in design implementation including datapath optimization, CTS, UPF and DFT instrumentation Sound knowledge in HDL including SystemVerilog and VHDL Exceptional debugging skills Proficiency in software and scripting skills (Perl, Tcl, Python) Experience in cross-functional teamwork, driving projects and mentoring Who You Are : Details oriented with a focus on maintaining high standards of product quality Excellent communication, organizational, risk assessment/mitigation, and time management skills Ability to abstract up and communicate meaningful conclusions and define next steps Excellent communication and leadership skills

What You'll Be Doing: * Designing and developing DDR I/O circuits to meet performance and power specifications. * Collaborating with cross-functional teams to integrate analog circuitry into SoCs. * Executing circuit design tasks with a focus on product quality and efficiency. * Conducting layout reviews and ensuring adherence to design methodologies. * Participating in design reviews and providing technical insights. * Staying updated with the latest advancements in CMOS processes and deep submicron technologies. The Impact You Will Have: * Enhancing the performance and efficiency of our silicon IP portfolio. * Contributing to the rapid integration of advanced capabilities into SoCs. * Reducing the time-to-market and risk for our customers products. * Driving innovation in analog design and setting new industry standards. * Strengthening Synopsys position as a leader in chip design and verification. * Empowering the development of high-performance, differentiated products. What You'll Need: * BTech/MTech in Electrical Engineering or a related field. * 4+ years of experience in CMOS circuit design and layout methodology. * Strong knowledge of deep submicron process technologies. * Familiarity with ASIC design flow and JEDEC standards for DDR interfaces. * Excellent written and verbal communication skills. Who You Are: * A collaborative team player with a proactive approach. * Detail-oriented with a commitment to quality and efficiency. * Innovative and adaptable, always seeking to learn and grow. * Effective communicator, able to convey technical information clearly.

What You'll Be Doing: Develop CMOS embedded memories such as SP SRAM, DP SRAM, Register File, and ROM. Design architecture and circuit implementation, focusing on ultra high speed, ultra low power, or high density designs. Perform schematic entry, circuit simulation, layout planning, layout supervision, design verification, and validation. Interface with CAD and Frontend engineers for memory compiler automation, EDA model generation, and full verification flow. Perform bit cell development and verification, and drive physical layout design and verification. Provide support and/or perform other duties as assigned and required. The Impact You Will Have: Contribute to the development of high-performance silicon chips and software content. Enhance the efficiency and performance of our CMOS memory designs. Drive innovation in ultra high speed, ultra low power, and high density memory designs. Ensure the highest quality in bit cell development and physical layout design. Collaborate effectively with CAD and Frontend engineers to streamline automation and verification processes. Support the continuous improvement and advancement of our memory design technology. What You'll Need: Bachelor's or Master's degree in Electrical Engineering, Telecommunication, or related fields. Proficiency in CMOS memory design, circuit simulation, memory layout designs, layout parasitic extraction, and layout verification tools and debugging techniques. Programming capability in C-Shell and Perl; knowledge of C++ or Java script is a plus. Strong analytical and problem-solving skills with attention to detail. Experience in developing documents, reports, or presentations for a range of tasks. Who You Are: Self-motivated, self-directed, detail-oriented, and well-organized. Possess excellent analytical, problem-solving, and negotiation skills. Capable of leading and mentoring trainees and junior engineers, as well as managing projects. Strong command of English, both verbal and written. Exhibit strong interpersonal communication and teamwork skills. Professional, critical/logical thinker, and focused on future goals. Highly committed to continuous learning and professional development.

What You'll Be Doing: Analyze various analog circuit techniques for dynamic and static power reduction, performance enhancement, and area reduction. Develop Analog Full custom circuit macros, including Transmitters, Receivers, Clocking circuits, equalizers, serializers, de-serializers, and Analog Front End needed for High-Speed PHY IP. Leverage your understanding of circuit design and layout, along with knowledge of bipolar, CMOS, passive structure, and interconnect failure modes. Collaborate with experienced teams locally and globally to deliver high-performance silicon chips. Create simulation environments to verify circuit specifications and debug circuits as needed. Optimize layouts and parasitics to enhance circuit performance and reliability. The Impact You Will Have: Contribute to the design and verification of advanced silicon chips, accelerating their development and manufacturing processes. Enable customers to optimize their chips for power, cost, and performance, significantly reducing project schedules. Drive innovations in high-speed physical interfaces, enhancing the performance and reliability of our products. Collaborate with global teams to leverage diverse expertise and deliver cutting-edge technology solutions. Influence the development of next-generation processes and models for manufacturing high-performance silicon chips. Ensure the successful implementation of analog and mixed-signal circuit designs in advanced CMOS technologies. What You'll Need: BE with 5+ years of relevant experience or MTech with 4+ years of relevant experience in Electrical/Electronics/VLSI Engineering or a related field. Strong fundamentals in CMOS circuit design, device physics, and sub-micron design methodologies. Experience with analog transistor-level circuit design in nanometer technologies. Familiarity with Multi Gbps range high-speed designs, including PAM4 serdes architectures. Proficiency in creating simulation environments and debugging circuits. Who You Are: Detail-oriented with excellent problem-solving skills. Strong communicator, capable of collaborating with teams across different locations. Innovative thinker with a passion for technology and circuit design. Proactive and self-motivated, with the ability to work independently and as part of a team. Adaptable and open to learning new techniques and methodologies.

Lead the deployment of Synopsys DFT technologies across key customer projects Act as the primary point of contact, facilitating smooth communication with customers and internal teams Define and manage project schedules, tracking milestones, and deliverables Identify potential risks early, escalate issues as needed, and ensure timely resolutions Ensure projects meet schedule, quality, and customer satisfaction benchmarks Collaborate with AE and R&D teams to meet technical and functional objectives Manage multiple project executions, ensuring seamless alignment with business goals Prepare and deliver progress updates and technical presentations to stakeholders The Impact You Will Have: Guarantee effective adoption of Synopsys DFT solutions in high-impact customer designs Enhance cross-functional team collaboration and ensure project alignment with business needs Contribute to Synopsys leadership in DFT implementation through timely and quality project deliveries Boost customer success and satisfaction with streamlined communication and delivery Proactively mitigate project risks, ensuring strong project health and stakeholder confidence What You'll Need: 510 years of experience with hands-on implementation of DFT technologies Strong expertise in Scan Compression, ATPG, LogicBIST, MemoryBIST, Boundary Scan Proven ability to manage multiple projects and deliver results under tight schedules Excellent communication, leadership, and organizational skills Proficiency in Microsoft Office tools (PowerPoint, Excel, Word) for documentation and reporting

Category Engineering Hire Type Employee Job ID 10335 Remote Eligible No Date Posted 26/03/2025 Alternate Job Titles: - Senior Digital Verification Engineer - Sr Staff ASIC Verification Engineer - Senior RTL Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: An experienced and passionate ASIC Digital Verification Engineer with a deep understanding of RTL-based IP cores and complex protocols. You have over 12 years of experience in functional verification and are adept at making architectural decisions for test bench designs. You are proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), and you have a proven track record of implementing coverage-driven methodologies. You bring a wealth of knowledge in protocols such as DDR, PCIe, AMBA, and more. Your technical expertise is matched by your strong communication skills, ability to work independently, and your innovative problem-solving capabilities. Your experience may also include familiarity with functional safety standards such as ISO26262 and FMEDA. What You'll Be Doing: Making architectural decisions on test bench design. Writing verification plans and specifications. Implementing test bench infrastructure and writing test cases. Implementing a coverage-driven methodology. Leading technical aspects of verification projects. Collaborating with international teams of architects, designers, and verification engineers. The Impact You Will Have: Enhancing the robustness and reliability of IP cores used in critical applications. Driving innovation in verification methodologies and tools. Ensuring high-quality deliverables through rigorous verification processes. Improving productivity, performance, and throughput of verification solutions. Contributing to the success of Synopsys customers in industries such as AI, automotive, and server farms. Mentoring and guiding junior engineers in the verification domain. What You'll Need: Knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI. Hands-on experience with UVM/VMM/OVM, test planning, and coverage closure. Proficiency in SystemVerilog and UVM, object-oriented coding, and verification. Experience with scripting languages like C/C++, TCL, Perl, Python. Experience with functional safety standards such as ISO26262 and FMEDA (preferred). Who You Are: Independent and precise in your work. Innovative and proactive in problem-solving. Excellent communicator and team player. Detail-oriented with a strong analytical mindset. Eager to learn and grow within a technical role. The Team You'll Be A Part Of: You will join the Solutions Group at our Bangalore Design Center, India. This team is dedicated to developing functional verification solutions for IP cores used in various end-customer applications. You will work closely with architects, designers, and verification engineers across multiple international sites, fostering a collaborative and innovative environment. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

What You'll Be Doing: Analyze various analog circuit techniques for dynamic and static power reduction, performance enhancement, and area reduction. Develop Analog Full custom circuit macros, including Transmitters, Receivers, Clocking circuits, equalizers, serializers, de-serializers, and Analog Front End needed for High-Speed PHY IP. Leverage your understanding of circuit design and layout, along with knowledge of bipolar, CMOS, passive structure, and interconnect failure modes. Collaborate with experienced teams locally and globally to deliver high-performance silicon chips. Create simulation environments to verify circuit specifications and debug circuits as needed. Optimize layouts and parasitics to enhance circuit performance and reliability. The Impact You Will Have: Contribute to the design and verification of advanced silicon chips, accelerating their development and manufacturing processes. Enable customers to optimize their chips for power, cost, and performance, significantly reducing project schedules. Drive innovations in high-speed physical interfaces, enhancing the performance and reliability of our products. Collaborate with global teams to leverage diverse expertise and deliver cutting-edge technology solutions. Influence the development of next-generation processes and models for manufacturing high-performance silicon chips. Ensure the successful implementation of analog and mixed-signal circuit designs in advanced CMOS technologies. What You'll Need: BE with 5+ years of relevant experience or MTech with 4+ years of relevant experience in Electrical/Electronics/VLSI Engineering or a related field. Strong fundamentals in CMOS circuit design, device physics, and sub-micron design methodologies. Experience with analog transistor-level circuit design in nanometer technologies. Familiarity with Multi Gbps range high-speed designs, including PAM4 serdes architectures. Proficiency in creating simulation environments and debugging circuits. Who You Are: Detail-oriented with excellent problem-solving skills. Strong communicator, capable of collaborating with teams across different locations. Innovative thinker with a passion for technology and circuit design. Proactive and self-motivated, with the ability to work independently and as part of a team. Adaptable and open to learning new techniques and methodologies.

Lead and execute Analog Mixed-Signal layout design for high-speed DDR/HBM IPs Deliver robust and high-quality physical layout designs ensuring adherence to DDR/HBM specs Apply deep understanding of FinFET and CMOS technology at 28nm and below Handle high-speed digital layout verification with attention to signal integrity Implement advanced floorplanning techniques and apply submicron mitigation strategies Coordinate with remote layout teams globally for layout quality and deliverables Drive internal flow adherence for tape-out readiness and schedule compliance Collaborate with PHY designers, package engineers, and system teams to meet design objectives Oversee IO layout requirements including bondpads, ESD, IR/EM, and DFM considerations Utilize physical verification tools and support Place & Route and top-level verification flows The Impact You Will Have: Shape next-gen high-speed memory interface solutions through expert physical design Ensure quality layout execution in advanced nodes, directly impacting performance and reliability Drive project delivery across global teams with technical leadership and coordination Enable Synopsys to meet customer demand in high-speed memory IPs with quality and timeliness Reinforce design flow adherence and process discipline to ensure tape-out success Contribute to the robustness of global layout practices through review and mentorship What You'll Need: 612 years of experience in Analog Mixed-Signal layout, specifically with DDR/HBM IPs Expertise in FinFET and CMOS layout at 28nm and below Strong knowledge of signal integrity, DRC/LVS/LPE, ESD/latchup, and IO pitch/layout constraints Familiarity with ASIC physical design flows including LEF, Place & Route, and verification Hands-on experience with advanced layout tools and scripting (Perl, TCL, etc. preferred) Proven leadership in global coordination and layout delivery Excellent communication and customer interaction skills

Category Engineering Hire Type Employee Job ID 10560 Remote Eligible No Date Posted 08/04/2025 Analog Design, Sr Engineer-10560 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced professional with a deep understanding of VLSI design and a strong background in high-speed protocols Analog Circuit Design - CMOS circuit design and layout methodology & flow. Familiarity with ASIC design flow. Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus. What You'll Be Doing: DDR/HBM Memory Interface I/O Circuit and layout design including GPIO and Special IO's. - Work with DDR/HBM PHY team, package engineers and system engineers to meet design specifications. What You'll Need: * Bachelor's and/or Master's Degree in Electrical Engineering or similar with a focus on VLSI design. * Experience Required: 1 - 3 yrs Who You Are: * Creative and results-oriented, capable of managing multiple tasks concurrently. * Strong verbal and written communication skills in English. * Ability to work collaboratively across teams to deliver solutions to customers. * Strong analytical, reasoning, and problem-solving skills. * Willingness to travel occasionally to support customer engagements. The Team You'll Be A Part Of: The team focuses on enabling our Interface IP customers to integrate the IP into their SoC and assist them through their design flows, debugging critical issues, and supporting silicon bring-up. This collaborative team works closely with customers to ensure the successful deployment of Synopsys leading Interface IP products in various market segments. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

What You'll Be Doing: Leading and mentoring a team of formal verification engineers to ensure high-quality IP delivery. Developing and driving formal verification plans, aligning with project timelines and IP deliverables. Defining test plans tailored to high-complexity digital IPs such as UFS MIPI Unipro I3C, AMBA, and other interconnect protocols. Identifying and implementing state-of-the-art formal verification methodologies and tools, including assertions, SystemVerilog Assertions (SVA), and custom verification environments. Driving innovation to enhance verification efficiency and coverage. Evaluating and mitigating verification risks early in the design phase to ensure IPs meet high-quality standards. The Impact You Will Have: Ensuring the robustness and quality of our digital design hardware IPs. Delivering best-in-class, verified IPs to semiconductor design companies globally. Enhancing verification efficiency and coverage through innovative methodologies. Mitigating verification risks early in the design phase, ensuring timely and high-quality IP releases. Contributing to the development of high-performance silicon chips and software content. Driving continuous technological innovation in chip design and verification. What You'll Need: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Advanced degrees preferred. 2 6 years of experience in formal verification of digital design IPs, with a strong track record in verifying complex IPs. Deep understanding of formal verification methodologies, including property-based and equivalence checking, SystemVerilog Assertions (SVA), and protocol compliance. Strong familiarity with industry-standard formal verification tools, such as Cadence JasperGold, Synopsys VC Formal, or Mentor Questa Formal. Extensive experience in digital design and verification for high-speed interconnect protocols. Who You Are: An excellent problem solver with a proactive approach to identifying and addressing verification challenges. A collaborative team player who thrives in a dynamic environment. An effective communicator who can lead and mentor junior engineers. An innovative thinker who drives continuous improvement in verification methodologies. A detail-oriented professional committed to delivering high-quality IPs.

Collaborate with cross-functional teams to define project scope, objectives, and deliverables Develop comprehensive project plans with clear timelines, milestones, and resource allocation Monitor project performance and proactively address delays, risks, and scope changes Communicate project progress, status updates, and risks to stakeholders and leadership Act as the R&D representative for customer engagements, ensuring project alignment and satisfaction Mentor and guide team members, promoting a culture of accountability, innovation, and collaboration Align execution strategies with senior leadership, escalate and resolve high-impact issues efficiently Identify areas for process improvement and integrate best practices for project delivery Utilize project management tools to track progress and ensure projects stay on budget and timeline The Impact You Will Have: Drive timely and successful execution of engineering programs, enhancing customer satisfaction Contribute to Synopsys innovation edge by ensuring well-coordinated delivery of complex projects Foster cohesive team environments and professional growth through mentorship and leadership Streamline cross-functional collaboration for better alignment and project outcomes Support business goals by ensuring high-quality, on-schedule, and within-budget delivery Champion process improvements that elevate project management standards What You'll Need: 815 years of experience leading complex engineering projects Bachelor's or Master's degree in Engineering or a related field Strong foundation in engineering principles and project life cycles Proven success in managing cross-functional project teams Exceptional communication and stakeholder management skills Proficiency in project tracking and planning tools (e.g., MS Project, Jira, Smartsheet)

Plan, organize, write, and edit various types of customer documentation. Collaborate with world-class engineers to create essential customer documentation in dynamic formats. Empower customers to design-in and optimize Synopsys products through clear, concise documentation. Translate complex technical information into user-friendly content. Ensure documentation meets industry standards and is easily accessible to global customers. Continuously update and maintain documentation to reflect product updates and new features. The Impact You Will Have: Enhance customer satisfaction by providing clear and comprehensive documentation. Facilitate the adoption and optimization of Synopsys products by global customers. Contribute to the overall success of Synopsys by ensuring high-quality documentation. Support the development of innovative solutions through effective communication. Help maintain Synopsys reputation as a leader in semiconductor IP and EDA software. Drive continuous improvement in documentation processes and standards. What You'll Need: Degree or master's in electronics, science, hardware, computing, software, physics, mathematics, or engineering discipline. Other technical disciplines also considered. 3-5 years of technical writing experience in the software or hardware industry. Excellent problem-solving skills and strong logical reasoning. Proficiency with authoring tools such as FrameMaker and Oxygen. Exceptional English writing and speaking skills.

Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc ) Generate verification test plan, verification environment documentation and test environment usage documentation Define, develop, and verify complex UVM verification environments Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics (functional coverage and code coverage) Collaborate with architect, designers, VIP team to accomplish tasks Identify design problems, possible corrective actions and/or inconsistencies on documented functionality Work with peers to improve methodologies and improve execution efficiency Adhere to quality standards and good test and verification practices Work as a lead, mentor junior engineers, and help them in debugging complex problems Support customer issues, by their reproduction and analysis Should be able to multitask between different activities Key Qualifications: Proven desire to learn and explore new state-of-the-art technologies Demonstrate good written and spoken English communication skills Demonstrate good review and problem-solving skills Knowledgeable with Verilog, VHDL and/or SystemVerilog Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus Understanding of verification methodology such as UVM Good organization and communication skills Be a solution provider 8+ years of relevant experience

Category Engineering Hire Type Employee Job ID 10209 Remote Eligible No Date Posted 30/03/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and initiative-taking individual with a strong technical background inPhysicaldesign,physicalverificationand STA at IP/block/full chip level implementation/methodology. You thrive in collaborative environments andpossessa passion for creating innovative technology. Yourexpertiselies in working with advancedFinfet and GAA process challenges, and you have a proactive analytical approach with a keen eye for detail. Your dedication to delivering high-quality results is complemented by excellent communication and people skills, allowing you to effectively collaborate with both internal teams and external customers. Driven by a desire to innovate, you are eager to contribute to the success of ourcutting-edgetechnology products. WhatYou'llBe Doing: * Conceptualizing, designing, and productizingstate-of-the-artRTLto GDS implementationfor SLM monitors realized through ASIC design flow. * Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics. * DevelopingDigital BE activities includessynthesis, pre-layout STA,SDCconstraints development, floor planning, bump placement, power planning, MV design techniques,VCLP, UPFunderstanding,placement, CTS, routingand collaborating with thedifferent functionalteamsto achieveoptimaldesign solutions. *Post layout STA,timing& functionalECOdevelopment, timingsignoffmethodologyat higher frequency IPdesignsclosure. * Physical verification, DRC, LVS, PERC, ERC, Antenna, EMIR, Power signoff. * Creating new flows/methodologies and updating existing ones through collaboration with architects and circuit design engineering teams. * Pre-layout and post-layout timing closure and timing model characterizations across various design corners to ensure reliability and aging requirements for Automotive & consumer products. The Impact You Will Have: * Accelerating the integration of next-generation intelligent in-chip sensors and analytics into technology products. *Optimizingperformance, power, area, schedule, and yield of semiconductor lifecycle stages. * Enhancing the reliability and differentiation of products in the market with reduced risk. * Driving innovation inPhysical design, physical verification, STA and signoffdesign methodologies and tools. * Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. * Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. WhatYou'llNeed: * BS/B.Techor MS/M.Techdegree in Electrical Engineering with 5+ years of relevant industry experience. * StrongPhysical design, physical verification,pre&post layoutSTA andEMIR/Powersignoffexperience, includingSDCdevelopment, UPF/Mutlivoltagedesigndevelopment experience. * Experience in DRC, LVS, DFM cleaning andtimingclosureis mandatory. * Proficiency with Digital design tool from any EDA vendor, preferably from Synopsys tools like FC/VCLP/PT/PT-PX/ICV and Redhawk * Sound understanding of Physical design, Physical verification and STA and signoff concepts. * Experience with design methodologies like developing custom scripts and enhancing flows for better execution. Experience in scripting with TCL/PERL is required. Who You Are: * Proactive and detail-oriented with excellent problem-solving skills. * Adept at working independently and providingphysical design and signoffsolutions. * Excellent communicator and team player, capable of collaborating effectively with diverse teams. * Innovative thinker with a passion for technology and continuous improvement. * Committed to delivering high-quality results and achieving project goals. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

BE / B. Tech / M. Tech or equivalent in Computer Science or Electronics Candidate will be part of word level Synthesis team (catering to multiple EDA products). Design, develop, troubleshoot the core algorithms. Will be working with local and global teams. Will be working on Synthesis QoR, Performance and logic interference problems It is a pure technical role. Will need to drive projects , solutions to complex problem with other team members Essential Skills: Ability to develop new software architecture and good leadership skills. Strong hands-on experience in C/C++ based software development. Strong background in Design Patterns, Data Structure, Algorithms, and programming concepts. Familiarity with multi-threaded and distributed code development. Familiarity with ASIC design flow and the EDA tools and methodologies used therein. Good knowledge of Verilog, SystemVerilog & VHDL HDL Well versed with Software Engineering and development processes Experience of production code development on Unix/Linux platforms. Exposure to developer tools such as gdb, Valgrind Exposure with source code control tool like Perforce. Good analysis and problem-solving skills. Desirable Skills: Work experience in Synthesis tools Work experience in EDA Experience in technically leading significant size projects

You Are: As an ideal candidate for the ASIC Digital Design Engineer, Senior role, you are a highly motivated and innovative individual with a deep understanding of ASIC development flow. You possess a strong theoretical and practical background in high-speed serializer and data recovery circuits. You are someone who thrives in dynamic environments and embraces the challenges that come with constant technological changes. You are self-motivated, proactive, and able to balance good design quality with tight deadlines. Your excellent communication skills enable you to interact seamlessly with different design groups and customer support teams. You are known for your ability to resolve issues creatively and exercise independent judgment in selecting methods and techniques to obtain solutions. You are a team player who can produce excellent results both as an individual and as part of a team. What You'll Be Doing: Developing and verifying digital designs for next-generation NRZ and PAM-based SerDes products. Running lint/cdc/rdc checks and synthesis flow. Working with Verilog and VCS to ensure design accuracy. Defining synthesis design constraints and resolving STA issues. Collaborating with mixed-signal engineers to deliver high-end mixed-signal designs from specification development to functional and performance tests. Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry. Enhancing the performance, power, and size efficiency of our silicon IP offerings. Enabling rapid market entry for differentiated products with reduced risk. Driving innovation in high-speed digital design and data recovery circuits. Supporting the creation of high-performance silicon chips and software content. Collaborating with a world-class team to solve complex design challenges. What You'll Need: BSEE or MSEE with a minimum of 2 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience with Verilog and VCS. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams. Self-motivated and proactive, with a strong attention to detail. A creative problem-solver who can think independently. Capable of working under tight deadlines while maintaining high-quality standards. A team player who can contribute effectively both individually and collaboratively.

What You'll Be Doing: Implementing state-of-the-art Verification environments for the DesignWare family of synthesizable cores. Performing Verification tasks for IP cores, focusing on domains such as USB, PCI Express, Ethernet, and AMBA. Collaborating closely with the RTL design team and other expert Verification Engineers globally. Engaging in Test planning, Test environment coding at both unit and system levels, Test case coding, and debugging. Coding and analyzing functional coverage and meeting quality metric goals. Managing regression processes to ensure comprehensive verification. The Impact You Will Have: Enhancing the robustness and reliability of our IP cores, ensuring high-quality deliverables. Contributing to the development of innovative solutions that drive the Era of Smart Everything. Reducing the time-to-market for our customers by ensuring their products meet performance, power, and size requirements. Supporting the integration of more capabilities into SoCs, enabling differentiated products. Participating in a global team effort to advance cutting-edge technologies in chip design and software security. Ensuring the successful verification of complex IP cores, contributing to the overall success and reputation of Synopsys. What You'll Need: BS/BE in Electrical Engineering with 5+ years of relevant experience or MS with 3+ years of relevant experience in IP core and/or SOC verification. Proficiency in developing HVL-based test environments and implementing test plans. Hands-on experience with industry-standard simulators such as VCS, NC, and MTI, and relevant debugging tools. Strong understanding of verification methodologies like UVM/VMM/OVM. Familiarity with Verilog and scripting languages such as Perl. Basic understanding of functional and code coverage. Excellent written and oral communication skills, along with strong analytical, debugging, and problem-solving abilities. Who You Are: A self-driven individual with a passion for technology and innovation. A collaborative team player with the ability to work effectively in a global team environment. A detail-oriented professional with a commitment to delivering high-quality work. A proactive learner who stays updated with the latest industry trends and technologies.