Pattern Data Analytics R&D Engineer (Sr.Staff)

Job Description

Collaborate with a cross-functional, multi-disciplinary team to identify new methodological approaches to layout analysis and define algorithmic solutions Develop software modules and shared libraries throughout a product life cycle, from prototype to customer release Implement testing and benchmarking automation for Pattern Analytics tools Coordinate the creation of engineering-level technical documentation for the supported products Troubleshoot and solve customer problems after deployment Stay updated with the latest advancements in EDA, data science, and machine learning to continuously enhance product offerings The Impact You Will Have: Drive innovations in semiconductor design and silicon manufacturing flows through advanced pattern analytics Enhance the efficiency and accuracy of layout analysis methodologies, contributing to the overall improvement of EDA tools Facilitate the development of cutting-edge computational solutions that address critical gaps in current industrial solutions Ensure the successful deployment and adoption of new EDA products by providing robust technical documentation and customer support Contribute to the continuous evolution of Synopsys product offerings, maintaining our leadership in the industry Empower semiconductor companies and software developers with innovative tools that streamline design and verification processes What You'll Need: Ph.D. or B.Tech/M.Tech in Electrical Engineering (EE), Computer Science (CS), or related fields, with a minimum of 5 years of industry experience Expertise in Python programming with a strong focus on data structures, advanced proficiency in libraries such as NumPy, Pandas, Matplotlib, Scipy, and development of new Python APIs or commands Extensive experience in C++ and/or Java Practical experience in developing Machine Learning models, including Graph Neural Network (GNN) models and LLM's type of models Knowledge in probability and statistics, Electronic Design Automation (EDA), VLSI Physical Design Verification, and/or Mask Data Generation