Category Engineering Hire Type Employee Job ID 10225 Remote Eligible No Date Posted 28/03/2025 R&D Engineering, Custom Circuit Architect Our Silicon Lifecycle Management (SLM) business is all about building next-generation intelligent in-chip sensors, hardware/software capabilities and analytics to integrate into technology products to manage and improve each semiconductor lifecycle stage. We offer the world's first full hardware IP, test, and end-to-end analytics to help customers integrate faster, optimize performance/power/area/schedule/yield, and enhance reliability. Meeting the unique challenges posed by various target applications, SLM enables differentiated products to market quickly with reduced risk. We are seeking an experienced, initiative-taking, and high-calibre individual to join our SLM Monitors group as a Monitor IP Design, Architect. Someone who thrives in a collaborative environment and has a passion for creating innovative technology. Have a strong technical background in Custom Circuit design, System Design, methodologies and tools and is adept at working with advanced finfet / GAA process challenges. Proactive analytical person with a keen eye for detail and a dedication to delivering high-quality results. Excellent communication and people skills and can collaborate effectively with internal teams and external customers. Driven by a desire to innovate and contribute to the success of our innovative technology products. Job Descriptions Looking forward towork on conceptualizing, designing and productizing state of the art Monitor IP to be used in SLM monitors realized though ASIC design flow. Work on Architecting sensing elements for on-chip Process, Voltage, Temperature, glitch and Droop monitors for monitoring silicon biometrics. You will be the part of SLM team. Individual should have strong technical experience in full custom mixed-signal circuit design, circuit simulations, working knowledge of custom layout, and pre-post-silicon characterization. Additional responsibilities include: Development of statistical simulation methodologies. Liaising with layout team to achieve best possible design solution. End to end ownership of the designed custom cells. Deployment of new circuits into test chips and post-silicon characterization Architecting new sensors and enhancing existing ones through collaboration with other architects and stakeholders. Building and refining design flows to enhance efficiency and effectiveness. Conducting pre and post-layout simulations and characterization across various design corners. Ensuring designs meet advanced finfet / GAA reliability and aging, reliability and Automotive grade requirements Working closely with the RTL, Verification and Physical Design teams for ensuing integration and Quality. Owning the product from Spec to Silicon report. Preferred skills: Strong custom design experience specification, circuit design description and schematics. Strong understanding of device Physics and Can work independently and debug and provide circuit solutions. Hands on experience with circuit design & simulation tools, IC design CAD packages from any EDA vendor Strong understanding of SPICE simulator concepts and simulation methods Familiar with circuit simulation tools like PrimeSim, FineSim, HSPICE or similar Must have prior experience with Custom Compiler or equivalent schematic & Layout editor tools Experience with statistical design methodology like generating and analyzing Monte-Carlo results Awareness of post-layout extraction & simulation, testing in conjunction with silicon validation Demonstrated technical expertise in the productization of advanced technologies. Job Requirements BS or MS degree in Electrical Engineering with 15+ years of relevant industry experience. Sound knowledge of custom / Standard cell design methodologies, layout tools, and physical verification. Familiarity with advanced finfet / GAA process challenges, simulation techniques and modeling. At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 10335 Remote Eligible No Date Posted 26/03/2025 Alternate Job Titles: - Senior Digital Verification Engineer - Sr Staff ASIC Verification Engineer - Senior RTL Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: An experienced and passionate ASIC Digital Verification Engineer with a deep understanding of RTL-based IP cores and complex protocols. You have over 12 years of experience in functional verification and are adept at making architectural decisions for test bench designs. You are proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), and you have a proven track record of implementing coverage-driven methodologies. You bring a wealth of knowledge in protocols such as DDR, PCIe, AMBA, and more. Your technical expertise is matched by your strong communication skills, ability to work independently, and your innovative problem-solving capabilities. Your experience may also include familiarity with functional safety standards such as ISO26262 and FMEDA. What You'll Be Doing: Making architectural decisions on test bench design. Writing verification plans and specifications. Implementing test bench infrastructure and writing test cases. Implementing a coverage-driven methodology. Leading technical aspects of verification projects. Collaborating with international teams of architects, designers, and verification engineers. The Impact You Will Have: Enhancing the robustness and reliability of IP cores used in critical applications. Driving innovation in verification methodologies and tools. Ensuring high-quality deliverables through rigorous verification processes. Improving productivity, performance, and throughput of verification solutions. Contributing to the success of Synopsys customers in industries such as AI, automotive, and server farms. Mentoring and guiding junior engineers in the verification domain. What You'll Need: Knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI. Hands-on experience with UVM/VMM/OVM, test planning, and coverage closure. Proficiency in SystemVerilog and UVM, object-oriented coding, and verification. Experience with scripting languages like C/C++, TCL, Perl, Python. Experience with functional safety standards such as ISO26262 and FMEDA (preferred). Who You Are: Independent and precise in your work. Innovative and proactive in problem-solving. Excellent communicator and team player. Detail-oriented with a strong analytical mindset. Eager to learn and grow within a technical role. The Team You'll Be A Part Of: You will join the Solutions Group at our Bangalore Design Center, India. This team is dedicated to developing functional verification solutions for IP cores used in various end-customer applications. You will work closely with architects, designers, and verification engineers across multiple international sites, fostering a collaborative and innovative environment. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

What You'll Be Doing: The Information Security Analyst will leverage multiple industry frameworks and regulatory standards including, but not limited to, ISO 27001, SOC 2 Type II, NIST 800-53, NIST CSF, GDPR, TISAX, SOX, etc. The Analyst will liaise with all business groups including Finance, Legal, Audit, HR, and other stakeholders globally to implement new solutions and processes as well as document and remediate outstanding issues. The Information Security Analyst will be responsible for security risk assessments of suppliers and partners external to Synopsys, assessments of systems within the organization, examine and rate risks, work with GRC tools and processes, and recommend risk mitigation controls. Responsibilities include: Identify, document, monitor, and report on risk register items, KPIs/KRIs, including the monitoring of security control efficacy. Demonstrate experience with governance, risk, and compliance tools Work with security control frameworks such as ISO 27001, SOC 2 Type II, NIST 800-53, NIST CSF, and similar Present security risks to wide audience such as risk owners and other stakeholders Demonstrate the ability to understand the end-to-end processes supporting IT, data, and security. Interacts with Synopsys IT and business stakeholders to understand risks to critical infrastructure by defining potential business impact with the responsibility to apply effective mitigation strategies. Provide guidance of control implementations related to governance frameworks, regulations, and corporate security policies Understanding of security functions including Incident Management, Change Management, Identity and Access Management, and Vendor Security Risk Management. Work closely within the Synopsys Information Security Team to detect potential security weaknesses and developing creative ways to handle challenges unique to the Synopsys business and systems architecture. Conduct third-party (vendor) risk assessments in collaboration with stakeholders. Provide security requirements to both internal partners and external third-party providers. Effectively communicate and work with a global team Maintain, enforce, and track the Synopsys Information Security Exception process. Stay current with industry, regulatory, and legal requirements relevant to security, compliance, and privacy. The Impact You Will Have: Enhance Synopsys overall security and compliance posture by building and improving the GRC portfolio. Enable and transform the risk management program to address the evolving cybersecurity threat landscape. Ensure regulatory compliance as the company continues to grow. Strengthen risk assessments of suppliers and partners, contributing to a robust security framework. What You'll Need: Bachelor's degree in Computer Science, Information Systems, or degree, or experience in a related field. Typically, 5-7 years of experience in a related field. Knowledge of common certification and attestation programs such as ISO 27001 and SOC 2 Type II, ISO 31000. Practical working experience with control frameworks like ISO 27001, NIST 800-53, SOC 2 Type II and NIST CSF. Excellent organizational skills with attention to detail and the ability to multitask for project prioritization.

Designing, automating, and supporting Linux systems and services in a 24/7 production environment. Independently and collaboratively evaluating, recommending, and implementing technical solutions to meet business needs. Collaborating with other technical teams to solve problems and continually evolve the technology. Troubleshooting issues to identify root causes and help unblock the customer. Preparing and maintaining documentation of systems, standards, configurations, and procedures. Supporting day-to-day operations including installation, configuration, maintenance, and troubleshooting of the engineering secure computing environment. Responding to alerts, reporting issues, escalating problems as required, and resolving significant matters using independent judgment within established support practices. Ensuring compliance with Synopsys security policies to protect stakeholder information. The Impact You Will Have: Maintaining the high-performance Synopsys Cloud environment, ensuring smooth operations and compliance with security policies. Contributing to the overall reliability and scalability of our cloud infrastructure. Enhancing customer satisfaction by resolving technical issues promptly and effectively. Driving continuous improvements in our technology and processes through collaboration and innovation. Ensuring the security and integrity of our systems through vigilant monitoring and maintenance. Supporting Synopsys mission to lead in chip design, verification, and IP integration by providing a robust and reliable cloud environment. What You'll Need: Extensive knowledge of Linux operating systems and security patching. Experience with installing, monitoring, and administering Linux systems (Ubuntu and RHEL primarily). One or more Linux System Administrator Certifications. Experience with monitoring and logging tools. Programming/Scripting skills in Shell/Python. Basic Networking fundamentals including TCP/IP, DNS, subnetting, and routing. Knowledge of networking for virtual machines, particularly regarding security and performance. Knowledge of remote desktop software solutions such as VNC, Citrix Xen server, and VDI. Solid knowledge of infrastructure services like Kickstart, NFS, DNS, and DHCP. Knowledge in Azure resources like VM, Network, NSG, and Blob Storage is a plus.

What You'll Be Doing: Collaborate with cross-functional teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuits. Create and optimize layout designs using industry-standard EDA tools. Perform physical verification and design rule checks to ensure design integrity and manufacturability. Participate in design reviews and provide feedback to improve design quality. Work closely with circuit designers to understand design specifications and constraints. Contribute to the development and enhancement of layout design methodologies and best practices. Stay updated with the latest industry trends and advancements in A&MS layout design. The Impact You Will Have: Ensure the highest quality and performance of our analog and mixed-signal integrated circuits. Drive innovation by developing cutting-edge layout designs that push the boundaries of technology. Enhance the manufacturability and reliability of our products through meticulous design and verification processes. Contribute to the overall success of our projects by providing valuable feedback during design reviews. Improve design methodologies and best practices, fostering a culture of continuous improvement. Support the growth and development of junior engineers by sharing your expertise and knowledge. What You'll Need: Bachelor's or Master's degree in Electrical Engineering or a related field. 2+ years of experience in A&MS layout design for integrated circuits. Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Excellent problem-solving and systematic skills. Ability to work effectively in a team-oriented environment. Good communication and interpersonal skills.

What You'll Be Doing: Develop CMOS embedded memories such as SP SRAM, DP SRAM, Register File, and ROM. Design architecture and circuit implementation, focusing on ultra high speed, ultra low power, or high density designs. Perform schematic entry, circuit simulation, layout planning, layout supervision, design verification, and validation. Interface with CAD and Frontend engineers for memory compiler automation, EDA model generation, and full verification flow. Perform bit cell development and verification, and drive physical layout design and verification. Provide support and/or perform other duties as assigned and required. The Impact You Will Have: Contribute to the development of high-performance silicon chips and software content. Enhance the efficiency and performance of our CMOS memory designs. Drive innovation in ultra high speed, ultra low power, and high density memory designs. Ensure the highest quality in bit cell development and physical layout design. Collaborate effectively with CAD and Frontend engineers to streamline automation and verification processes. Support the continuous improvement and advancement of our memory design technology. What You'll Need: Bachelor's or Master's degree in Electrical Engineering, Telecommunication, or related fields. Proficiency in CMOS memory design, circuit simulation, memory layout designs, layout parasitic extraction, and layout verification tools and debugging techniques. Programming capability in C-Shell and Perl; knowledge of C++ or Java script is a plus. Strong analytical and problem-solving skills with attention to detail. Experience in developing documents, reports, or presentations for a range of tasks. Who You Are: Self-motivated, self-directed, detail-oriented, and well-organized. Possess excellent analytical, problem-solving, and negotiation skills. Capable of leading and mentoring trainees and junior engineers, as well as managing projects. Strong command of English, both verbal and written. Exhibit strong interpersonal communication and teamwork skills. Professional, critical/logical thinker, and focused on future goals. Highly committed to continuous learning and professional development.

Specify, design, and implement state-of-the-art verification environments for the DesignWare family of synthesizable cores. Perform verification tasks for IP cores, working closely with RTL designers. Drive ownership of critical areas of verification along with a team of talented verification engineers. Manage and own a team to develop and implement advanced test plans and test environments at both unit and system levels. Code and debug test cases, implementing complex checkers and assertions. Extract and review functional coverage (FC) and code coverage metrics, ensuring quality metric goals are met. Manage regressions and contribute to the continuous improvement of verification strategies and test environments. The Impact You Will Have: Enhance the quality and efficiency of our verification processes, ensuring robust and reliable IP cores. Contribute to the development of cutting-edge technologies that power the Era of Smart Everything. Enable the creation of high-performance silicon chips and software content, driving innovation in various industries. Collaborate with a global team of experienced verification engineers, fostering a culture of knowledge sharing and continuous learning. Play a key role in the success of Synopsys DesignWare IP Verification R&D team, contributing to our leadership in chip design and software security. What You'll Need: BS/MS in Electrical Engineering or Electronics and Communication Engineering with 10+ years of relevant experience. Proven experience in developing HVL (System Verilog/UVM) based test environments. Expertise in developing and implementing test plans, checkers, and assertions. Proficiency in extracting verification metrics such as functional coverage and code coverage. Experience with memory interface protocols (DDR, LPDDR) and IP design and verification processes.

Category Engineering Hire Type Employee Job ID 10431 Remote Eligible No Date Posted 03/04/2025 Sr. Staff- ASIC Verification. This is a verification focused individual contributor's role. The candidate will be part of the DesignWare IP Verification R&D team at our Bangalore Design Center, India. Implement state-of-the-art Verification environments for the DesignWare family of synthesizable cores and perform Verification tasks for the IP cores. Work closely with RTL design team and be part of a global team of expert Verification Engineers. Domains will include but not be limited to USB, PCI Express, Ethernet,AMBA. Job role will have a combination of Test planning, Test environment coding both at unit level and system level, Test case coding and debugging, FC coding and analysis and meeting quality metric goals and regression management. Requirements: - BS/BE in EE with 8+ years of relevant experience or MS with 6+ years of relevant experience in the verification of IP cores and/or SOC verification. - Experience in developing HVL based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage. - HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and relevant debugging tools. - Exposure to verification methodologies such as UVM/VMM/OVM is required. - Familiarity with HDLs such as Verilogand scripting languages such as perl is highly desired. - Exposure to IP design and verification processes including VIP development is an added advantage. - Basic understanding of functional & Code coverage. - It is essential that the individual has good written and oral communication skills and is able to demonstrate good analysis, debug and problem solving skills and be self-driven. Our Silicon IP business is all about integrating more capabilities into an SoCfaster. We offer the world's broadest portfolio of silicon IPpredesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're poweringit all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a proactive and detail-oriented individual with a passion for People Operations. With 0 - 2 years of experience in HR operations, you have a solid foundation in managing the employee lifecycle from pre-onboarding through offboarding. Your experience with HRIS systems, ServiceNow, particularly SuccessFactors or similar tools, equips you with the skills to handle complex employee data and processes. You hold a BA/BS degree and have honed your ability to manage multiple tasks and deadlines with exceptional organizational skills. Your strong stakeholder partnering skills enable you to collaborate effectively with various teams, ensuring the delivery of impactful HR solutions. You are familiar with Microsoft Office and project management tools, and your excellent written and spoken communication skills make you a reliable and clear communicator. Your resourceful problem-solving abilities allow you to troubleshoot issues independently and drive meaningful solutions. What You'll Be Doing: Collaborate effectively with stakeholders to proactively determine and deliver relevant and impactful People (HR) operation solutions to business and system challenges. - Accurately perform employee lifecycle transactions/processes, including onboarding, offboarding, transfers/job status changes, timekeeping, time off and leave, extended workforce, and other responsibilities as assigned. - Recommend and draft employee lifecycle processes and procedures that enhance and optimize existing HR practices, ensuring they remain fit for purpose and benefit stakeholder teams. - Be a trusted resource for People (HR) systems, data, and process knowledge to interpret and analyze processes. - Drive People operation enhancements by supporting new module roll-out and optimization initiatives. - Manage requests, workflows, and develop a knowledge base and reporting metrics using ServiceNow. The Impact You Will Have: Streamline HR processes to improve efficiency and accuracy in employee lifecycle management. - Enhance stakeholder satisfaction by delivering timely and effective HR solutions. - Contribute to the optimization of HR practices, ensuring they are aligned with organizational goals. - Support the successful rollout and adoption of new HR modules and tools. - Provide valuable insights and data analysis to drive informed decision-making in HR operations. - Foster a collaborative and supportive HR environment, building trust with stakeholders and team members. What You'll Need: 0 - 2 years of People (HR) operations related APAC work experience. - BA/BS degree. - Experience with HRIS administration, particularly SuccessFactors or similar tools. - Knowledge of managing requests, workflows, developing knowledgebase, and reporting metrics using ServiceNow. - Exceptional organizational skills and attention to detail. - Proficiency in Microsoft Office suite and familiarity with project management tools. - Excellent written and spoken communication skills. Who You Are: Detail-oriented and organized. - Resourceful problem-solver. - Effective communicator. - Collaborative team player. - Proactive and initiative-driven. The Team You'll Be A Part Of: You will be part of a dynamic People Operations team focused on delivering exceptional HR services and solutions. Our team collaborates closely with various stakeholders to ensure smooth HR operations and continuous improvement of HR processes. We value innovation, teamwork, and a commitment to excellence in all our endeavors. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 10442 Remote Eligible No Date Posted 03/04/2025 Job role: At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon IP business is all about integrating more capabilities into an SoCfaster. We offer the world's broadest portfolio of silicon IPpredesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. We're looking for ASIC Digital Verification Engineers with different experience levels to join the team! Does this sound like a good role for you You will be working on VLSI IP verification of controllers related to complex protocols.You will be part of the Solutions Group at our Bangalore Design Center, India. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Verification domain. Job Responsibilities - Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design for some of the components of the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as Ethernet/DSC/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/DDR/PCIe/ USB/ MIPI Be an individual contributor in the Verification Tasks Architect testbenches, coding of TE, debug, verification coverage improvement, etc. Will contribute to technical review of TE Code of medium complexity. Will contribute to technical process and quality improvement to achieve high quality deliveries Will be expected to Solve complex/ abstract problems The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in CRV environment. The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide. May need to take the role of technical lead for a few of the components of the Test Environment and achieve high quality verification with a small team of verification engineers. The role offers ample scope to mentor junior engineers and interns and to enhance ones leadership skills. Key Qualifications and Experience Must have BSEE/ MSEE in EE with 5 to 8 years of relevant experience in the following areas: Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc. Knowledge of one or more of protocols: Ethernet/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/USB/ DDR/PCIe MIPI/DSC. Knowledge of Ethernet protocol will be plus. Hands on experience with creating detailed design of components of Test Environment from Functional Specifications/ Test Environment Specifications. The TE must have used methodologies such as UVM, OVM Test Planning, Coverage Planning, Assertion Planning Hands on experience with System Verilog coding and Simulation tools; Deep Knowledge of OOPs Concepts Experience with Perforce or similar revision control environment Knowledge of Perl/Shell scripts. Exposure to quality processes in the context of IP design and verification is an added advantage In addition, the candidate should have good communication skills, will be a team player, and will have good problem-solving skills. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

The candidate will be part of the Static Verification team, a group of talented engineers dedicated to developing and enhancing platform for our static verification products. This team collaborates closely with other departments, including design, development, and customer support, to ensure seamless integration and execution. Together, the candidate will work on cutting-edge projects that push the boundaries of technology and contribute to the success of Synopsys and its customers. Person will work in platform team of static verification. Platform team provides support to various apps which are part of static verification. The hired candidate will provide features and support needed for successful deployment and ongoing business for apps of static verification. He might also work in developing GenAI application related to static platform. Technical competencies required for the role Strong hands-on experience in C/C++ based Object Oriented large and complex enterprise software development. Strong background in Design Patterns, Data Structure, Algorithms , and programming concepts. Well versed with Software Engineering and development processes. Experience with popular AI/ML frameworks (e.g., TensorFlow, PyTorch) is desirable. Experience with production code development on Unix/Linux platforms. Ability to develop new architectures and demonstrate strong leadership skills. Ability to troubleshoot, debug, and support software applications. Good analysis and problem-solving skills. 4+ years of software development experience. Preferable skills Experience in EDA/AI/ML research and development Exposure to Tcl, Python, Shell scripting and/or Vim Exposure to developer tools such as gdb, Valgrind,Visual Studio and Eclipse. Exposure with source code control tool like Perforce, Clearmake, CVS or Git . At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Design DDR/HBM memory interface I/O circuits and layouts, including GPIO and special I/Os Collaborate with PHY, package, and system engineering teams to meet interface specifications Ensure high-quality analog design through adherence to proven circuit and layout practices Participate in design reviews and support continuous improvement initiatives Stay updated on analog design technologies and implement relevant innovations Document the design process and assist in validation and testing activities The Impact You Will Have: Improve the performance and reliability of analog/mixed-signal circuits Drive high-quality development of DDR/HBM memory interfaces Support successful SoC integration and silicon realization Contribute to innovations in analog design and methodology Help maintain Synopsys position as a market leader in semiconductor IP What You'll Need: Bachelor's or Master's degree in Electronics/Electrical Engineering 13 years of experience in CMOS and deep submicron process technologies Proficiency in circuit design and layout methodologies for analog/mixed-signal blocks Basic understanding of analog circuit principles and mixed-signal environments Familiarity with ASIC flows and JEDEC DDR interface requirements

An Analog Design engineer works on conceptualizing, designing and productizing state of the art analog sensors. We are seeking an experienced, highly motivated, and high-caliber individual to work on design of on-chip Process, Voltage, Temperature, Current and Droop sensors as part of PVT sensor group. This individual should have strong technical experience in full custom analog/mixed-signal circuit design, circuit simulations, custom layout and post-silicon characterization. Additional responsibilities include: Development of new solutions in the field of on-die monitoring Liaising with layout team to achieve best possible engineering solution Deployment of new sensors into test chips and post-silicon characterization Guiding more junior engineers and tracking their work Job Requirements Design oriented and forward-looking thought process Sound knowledge of custom Analog/AMS design techniques, implementation and verification B.Tech. or M.Tech. degree in Electrical Engineering with 5+ years of relevant industry experience or Phd with relevant experience. Awareness of full custom layout techniques Exposure to advanced process challenges, including ESD and Reliability Exposure to architecture, design and verification of PVT, Oscillators, Bandgap, PLLs, LDOs, ADCs, Amplifiers, PHYs and other Mixed-signal blocks Excellent teamwork, communication, mentoring, and interpersonal skills with both internal teams and external customers Preferred skills : Strong custom design experience specification, circuit design description and schematics Hands on experience with circuit design & simulation tools, IC design CAD packages from any EDA vendor Strong understanding of SPICE simulator concepts and simulation methods Familiar with circuit simulation tools like PrimeSim, FineSim, HSPICE or similar Must have prior experience with Custom Compiler or equivalent schematic & Layout editor tools Experience with statistical design methodology like generating and analyzing Monte-Carlo results Awareness of post-layout extraction & simulation, testing in conjunction with silicon validation Demonstrated technical expertise in the productization of advanced technologies

What You'll Be Doing: Developing and maintaining automation pipelines and shared libraries in GitLab and Jenkins to support CI/CD flows for ARC products. Collaborating with R&D teams to implement efficient automation flows for automated building, regression testing, deployment, and advanced reporting. Providing extensive support and automation consulting to users of the continuous integration ecosystem. Ensuring the stability and efficiency of CI/CD pipelines through rigorous testing and optimization. Creating and maintaining detailed documentation of automation processes and best practices. Working closely with engineering and verification teams across multiple global sites to align on automation strategies and improvements. The Impact You Will Have: Enhancing the efficiency and reliability of CI/CD processes for Synopsys ARC products. Improving the overall productivity of engineering and verification teams through effective automation solutions. Ensuring high-quality software releases by developing robust automation pipelines. Contributing to the continuous improvement of automation practices and tools within the organization. Facilitating faster and more reliable deployment of new features and updates. Supporting the global collaboration efforts by providing consistent and reliable automation infrastructure. What You'll Need: Engineering or master's degree in Computer Science or Electrical Engineering (or equivalent). Solid practical experience in build/test automation (Jenkins pipeline, GitLab CI). Proficiency in general-purpose scripting languages (e.g., Python, Bash, Groovy). Experience with build tools (e.g., Make, CMake, Ninja). Skills in source code management tools (Git is a must, Perforce would be beneficial). Good understanding of Docker. User experience with Unix/Linux systems. Knowledge in DevOps and CI/CD web-services and tools (e.g., Artifactory, Ansible, Grafana). Good level of both verbal and written English.

Working on producing highly optimized hardware IP for the ARC family of configurable processors. Collaborating with an international multi-disciplinary team on the qualification, benchmarking, and test chip implementation of new microprocessor IPs. Participating in in-house test chip designs and development platforms to learn about potential applications of our microprocessor IPs. Assisting in customer sales and design-ins of our IP, providing technical support and expertise. Implementing a comprehensive implementation flow that is configurable and supported by Synopsys memory compilers and standard cell libraries. Ensuring the highest standards of quality in physical verification and IR processes. The Impact You Will Have: Contributing to the development of cutting-edge microprocessor IPs that set industry standards. Enhancing the capabilities of our customers by enabling them to develop highly sophisticated embedded designs. Driving the success of our products through your expertise in physical verification and IR. Supporting our sales team by providing technical insights and facilitating design-ins. Improving the efficiency and configurability of our implementation flows. Helping to position Synopsys as a leader in the semiconductor industry through continuous innovation. What You'll Need: Bachelor's degree in electronics engineering or computer science; Master's degree is a plus. Minimum of 5 years of related experience in physical verification and IR. Proficiency in Verilog/VHDL. Expertise in Unix, Perl, and TCL scripting. Understanding of microprocessor design is highly desirable.

What You'll Be Doing: Supporting development and verification of ASIC digital designs for next-generation NRZ and PAM-based SerDes products. Setting up and running lint/cdc/rdc checks using VC-Spyglass and synthesis flow using Design Compiler/Fusion Compiler. Working with Verilog and VCS to ensure design accuracy. Defining synthesis design constraints and resolving STA issues. Setting up and running FPGA prototyping flows to map RTL designs to Xilinx FPGAs. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry. Enhancing the performance, power, and size efficiency of our silicon IP offerings. Enabling rapid market entry for differentiated products with reduced risk. Driving innovation in high-speed digital design and data recovery circuits. Supporting the creation of high-performance silicon chips and software content. Collaborating with a world-class team to solve complex design challenges. What You'll Need: BSEE or MSEE with a minimum of 2 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience in coding, verifying Verilog and System Verilog design. Experience of working with minimum supervision and owning and delivering for front-end activities in IP/SOC. Experience of leading technically for front-end activities. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams. Self-motivated and proactive, with a strong attention to detail. A creative problem-solver who can think independently. Capable of working under tight deadlines while maintaining high-quality standards. A team player who can contribute effectively both individually and collaboratively.

Design and develop DDR I/O circuits targeting high performance and low power consumption Collaborate with cross-functional teams to efficiently integrate silicon IP into SoCs Perform circuit simulations and layout verification to ensure design precision Interface with internal engineering teams to troubleshoot and resolve design challenges Stay abreast of technological advancements and evolving industry standards (e.g., JEDEC) Document design methodologies for process improvement and knowledge sharing The Impact You Will Have: Propel next-gen silicon IP development with robust DDR I/O solutions Improve SoC integration speed and efficiency, aiding rapid product launches Advance innovation in chip design for smart technologies Ensure product quality meets or exceeds industry benchmarks Support Synopsys leadership in high-performance silicon IP Enable effective collaboration across expert engineering teams What You'll Need: BTech/MTech in Electrical Engineering or related discipline 3+ years of experience (MTech) or 5+ years (BTech) in CMOS circuit design and layout Strong grasp of deep submicron technologies and layout methodology Knowledge of JEDEC DDR interface standards Familiarity with ASIC design flow and ESD concepts is a plus Excellent problem-solving, analytical, and communication skills

You Are: You are a highly motivated and detail-oriented verification engineer with a passion for ensuring the functionality and reliability of advanced semiconductor technologies. You possess a strong background in digital verification and have a keen understanding of analog and mixed-signal (AMS) verification flows. With 4-8 years of experience in design and verification for leading-edge Digital SOC chip design and IP development, you bring expertise in areas such as Digital Verification, AMS Verification with Verilog A, and RNM (Real Number Modeling). You thrive in a collaborative environment, working seamlessly with cross-functional teams to achieve top-level integration and verification goals. You are committed to continuous learning and eager to take on technical leadership roles, guiding teams to intercept TQV and other swim lanes for top-level integrations. Your knowledge of System Verilog, foundry PDKs, and SOC Design flow sets you apart, and you are ready to contribute to the success of Synopsys Sensor IP business unit. What You'll Be Doing: Leading the digital verification flow for PVT Sensor Digital Verification. Setting up and managing AMS Verification and front-end Integration for MSIPs. Developing and supporting next-generation analog, digital, and mixed-signal IPs. Ensuring all blocks are verified for behavioral and functionality from top-level integration. Collaborating with a team to intercept TQV and other swim lanes for top-level integrations. Implementing mixed-mode simulations with significant improvements in execution time. The Impact You Will Have: Enhancing the reliability and performance of semiconductor lifecycle management solutions. Accelerating the integration of intelligent in-chip sensors and analytics capabilities. Optimizing performance, power, area, schedule, and yield for cutting-edge technology products. Reducing risk and time-to-market for differentiated products. Contributing to the development of Synopsys next-generation analog, digital, and mixed-signal IPs. Supporting the growth and success of Synopsys Sensor IP business unit. What You'll Need: BS or MS degree in Electrical Engineering, Computer Science, or Computer Engineering. 4-8 years of experience in design and verification for leading-edge Digital SOC chip design and IP development. Expertise in Digital Verification and/or AMS Verification with Verilog A and RNM. Proficiency in System Verilog and RNM (Real Number Modeling). Understanding of latest foundry PDKs and their usage in FE & BE flows. Who You Are: A detail-oriented and highly motivated verification engineer. A collaborative team player with excellent communication skills. A continuous learner eager to stay updated with industry trends and technologies. A leader capable of guiding and mentoring teams to achieve verification goals. A problem-solver with strong analytical and debugging skills.

What You'll Be Doing: Defining and developing ASIC RTL verification at both chip and block levels. Creating and executing verification plans for complex digital designs, particularly focusing on PCIe/CXL protocols. Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. Utilizing advanced verification methodologies and tools to achieve high-quality results. Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement. Communicating with internal and external stakeholders to align on project goals and deliverables. The Impact You Will Have: Enhancing the reliability and performance of Synopsys digital verification processes. Improving time-to-market for robust Synopsys Interface IP controller through efficient verification methodologies. Mentoring and nurturing a highly skilled verification team, elevating overall project quality. Influencing strategic decisions that shape the future of Synopsys capabilities. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements. What You'll Need: Extensive experience in ASIC RTL verification. In-depth knowledge of PCIe, CXL , UCIe and similar IO protocols. Proficiency in advanced digital design verification tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 18+ years in relevant domain. Who You Are: A mentor who fosters talent and encourages innovation. A proactive problem solver who thrives in complex environments. An effective communicator with the ability to convey technical concepts to a broad audience. A team player who values collaboration and diversity.

What You'll Be Doing: Designing and validating custom standard cells, including flip flops, clock gating cells, level shifters, and power gating cells. Optimizing standard cell circuits to achieve better performance, power, and area (PPA). Engaging in hands-on development while mentoring and coaching junior R&D engineers. Collaborating with layout designers to optimize layout parasitics and achieve target PPA. Involving in layout extraction and understanding layout-dependent parameters in the extracted netlist. Implementing, testing, and analyzing circuit design guidelines and methodologies. The Impact You Will Have: Driving innovations in standard cell design that contribute to the success of Synopsys products. Enhancing the performance, power, and area (PPA) of our silicon IP portfolio. Mentoring and developing the next generation of R&D engineers. Collaborating across functions to ensure methodology alignment and optimization. Contributing to the continuous improvement of circuit design methodologies. Supporting the integration of more capabilities into System-on-Chip (SoC) designs, meeting unique performance, power, and size requirements. What You'll Need: Bachelor's or Master's degree in Electrical Engineering or a related field. 10+ years of experience in standard cell library design. Deep understanding of CMOS device characteristics and submicron process nodes. Experience with FINFET/GAA technologies and high sigma variation analysis. Familiarity with layout design and optimization of layout parasitics. Who You Are: Strong analytical and logical skills. Effective communicator and collaborator. Proactive problem solver with a hands-on approach. Mentor and coach for junior engineers. Innovative thinker with a passion for technology.