Staff Formal Verification Engineer

Job Description

Staff Silicon Formal Verification Engineer :- Bangalore Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon Silicon Formal Verification Engineer Job Description In this role you will be responsible for developing and applying formal verification techniques to ensure functional correctness and completeness of high performance AI/ML Chiplet and SiP products. You will collaborate with a team of highly skilled team Architects and RTL Design engineers to identify, define, and verify components suited for formal analysis. Create robust formal abstract models to verify system-level properties, such as deadlocks, livelocks, anti-starvation, coherency. Innovate by integrating formal methods with simulation-based techniques to enhance bug detection efficiency. Develop scalable and reusable proof methodologies to support the verification process. Technical Requirements In-depth knowledge in formal verification algorithms, methods and use cases Expert user of formal verification tools (JasperGold, VC Formal, Questa Formal tools) Expertise in system Verilog assertion and abstract model development Hands on experience as Formal verification Engineer on AI or CPU designs. Comprehensive knowledge of computer architecture and familiarity with x86 or ARM or RISC processors:- Job Description In this role you will be responsible for developing and applying formal verification techniques to ensure functional correctness and completeness of high performance AI/ML Chiplet and SiP products. You will collaborate with a team of highly skilled team Architects and RTL Design engineers to identify, define, and verify components suited for formal analysis. Create robust formal abstract models to verify system-level properties, such as deadlocks, livelocks, anti-starvation, coherency. Innovate by integrating formal methods with simulation-based techniques to enhance bug detection efficiency. Develop scalable and reusable proof methodologies to support the verification process. Technical Requirements In-depth knowledge in formal verification algorithms, methods and use cases Expert user of formal verification tools (JasperGold, VC Formal, Questa Formal tools) Expertise in system Verilog assertion and abstract model development Hands on experience as Formal verification Engineer on AI or CPU designs. Comprehensive knowledge of computer architecture and familiarity with x86 or ARM or RISC processors Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"