STA Engineer (Static Timing Analysis)

As an STA Engineer with at least 4 years of experience, you will be responsible for netlist and constraint sign-in checks and validation. You will be involved in Prime Time constraint generation and development at the top level, full chip level, and clean up. Your expertise in multimode multi-corner timing knowledge will be crucial for timing closure at sub HM/block/top level. You will also be involved in top-level timing closure with sign-off STA in MMMC with Xtalk and OCV. Additionally, you will play a key role in top-level ECO implementation strategy development for netlist, RTL, and timing level changes. Proficiency in scripting languages such as Perl and TCL will be essential for this role. If you are someone who prefers immediate joiner or has a less notice period, this opportunity based in Bangalore/Hyderabad/Pune could be the next step in your career. Regards, Sneha sneha.s@acldigital.com,