Job
Description
You will work as a DV Engineer with a focus on SOC design verification at Qualcomm India Private Limited. Your responsibilities will include understanding internal requirements and complexities of auto, compute, mobile, XR-VR, IoT SOCs, and architecting the required verification strategy. You will set up methodologies, develop test plans, and ensure that the design meets the highest quality standards. Early involvement in the product life-cycle is emphasized, including participating in architecture/product definition. **Key Responsibilities:** - Define verification architecture, develop test plans, and build verification environment - Work with the design team to understand design intent and establish verification plans and schedules - Verify Subsystems and Full SoC using advanced verification methodologies - Build agents and checkers from scratch and write test plans based on design architecture specs and/or protocol standard - Develop test plans to verify all low power aspects across all modes of verification (RTL, PA-RTL, PA-GLS, and Formal) - Own end-to-end DV tasks from coding Testbench and test cases, write assertions, debugging UPF and RTL, and achieve all coverage goals - Assist in silicon bring-up, debug, and bring-up activities **Qualifications Required:** - B.E/B.Tech/M.E/M.Tech in Electronics with 5+ years of experience in the verification domain - Strong fundamentals in digital ASIC verification - Experience in IP/SS/SoC level verification of medium to high complexity design - Familiarity with system-level HW and SW Debug techniques and verification requirements - Good understanding of the complete verification life cycle (test plan, testbench through coverage closure) - Strong System Verilog/UVM based verification skills and experience with Assertion & coverage-based verification methodology - Experience with PSS or higher-level test construction languages is an added advantage - Working knowledge of Interconnect architecture and Bus protocols like AMBA - ACE/CHI/AXI - Good understanding of low power design techniques - Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells, and state retention cells - Experience with UPF/CPF based power-aware verification - Working knowledge of GLS, PAGLS, and scripting languages such as Perl, Python is a plus - Prior work on NoC/Interconnects end-to-end verification with a solid understanding of Bus protocols, Coherency, Performance, Latency, clock gating, etc. - Knowledge of one or more of Multimedia design blocks such as Display/Camera/Video/GFx - Knowledge of one or more of peripheral blocks verification such as PCIe/USB/UFS/I3C **Note:** Qualcomm is an equal opportunity employer that provides accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you may contact disability-accommodations@qualcomm.com or Qualcomm's toll-free number. You will work as a DV Engineer with a focus on SOC design verification at Qualcomm India Private Limited. Your responsibilities will include understanding internal requirements and complexities of auto, compute, mobile, XR-VR, IoT SOCs, and architecting the required verification strategy. You will set up methodologies, develop test plans, and ensure that the design meets the highest quality standards. Early involvement in the product life-cycle is emphasized, including participating in architecture/product definition. **Key Responsibilities:** - Define verification architecture, develop test plans, and build verification environment - Work with the design team to understand design intent and establish verification plans and schedules - Verify Subsystems and Full SoC using advanced verification methodologies - Build agents and checkers from scratch and write test plans based on design architecture specs and/or protocol standard - Develop test plans to verify all low power aspects across all modes of verification (RTL, PA-RTL, PA-GLS, and Formal) - Own end-to-end DV tasks from coding Testbench and test cases, write assertions, debugging UPF and RTL, and achieve all coverage goals - Assist in silicon bring-up, debug, and bring-up activities **Qualifications Required:** - B.E/B.Tech/M.E/M.Tech in Electronics with 5+ years of experience in the verification domain - Strong fundamentals in digital ASIC verification - Experience in IP/SS/SoC level verification of medium to high complexity design - Familiarity with system-level HW and SW Debug techniques and verification requirements - Good understanding of the complete verification life cycle (test plan, testbench through coverage closure) - Strong System Verilog/UVM based verification skills and experience with Assertion & coverage-based verification methodology - Experience with PSS or higher-level test construction languages is an added advantage - Working knowledge of Interconnect architecture and Bus protocols like AMBA - ACE/CHI/AXI - Good understanding of low
