SMTS STA / Synthesis Engineer

As a member of the AECG ASIC Group, you will help bring to life cutting-edge designs. As a member of the Back-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
• Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA
• we'll versed with timing signoff methodology and corner definitions
• Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks
• Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts)
• Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip.
• Ensuring full chip level Interface timing closure along DRV closure
• Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure

PREFERRED EXPERIENCE:

• 12+ years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.
• Successfully led static timing analysis (STA) and closure for 2 3 SoC projects from RTL to tape-out.
• Proficient in analyzing SoC architecture to derive appropriate timing constraints and define STA methodology.
• Skilled in translating architectural and design specifications into accurate timing constraints (SDC), including clock definitions, generated clocks, exceptions (false paths, multi-cycle paths), and hierarchical timing.
• Coordinated cross-functional efforts across design, synthesis, P&R, and verification teams to ensure timing signoff.
• Owned timing budgets, constraint development, and timing ECOs, achieving first-pass silicon success.
• Experience with analyzing the timing reports and identifying both the design and constraints related issues.
• Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc
• Excellent communication and interpersonal skills and always enthusiastic to collaborate with diverse teams.
• Experience in timing closure of high frequency blocks & subsystems (> Ghz range )
• Experience in working full-chip STA closure, defining mode requirements and corners for timing closure.
• Strong Understanding of DFT modes requirements for timing signoff
• Good understanding of physical design flow and ECO implementation.
• Strong understanding of SDC constraints, OCV,AOCV,POCV analysis.
• Strong TCL/scripting knowledge is mandatory.

ACADEMIC CREDENTIALS:

• Bachelors orMastersdegree in computer engineering/Electrical Engineering