Signoff and Circuit Methodology Engineer

As a Hardware Testing Engineer at Google, you will play a crucial role in ensuring the reliability of Google's custom-designed machines, which form an integral part of a vast and powerful computing infrastructure. In this role, you will be responsible for designing test equipment for prototypes of cutting-edge machinery in the R&D lab and developing protocols to scale these tests for the global team. Collaborating closely with design engineers, you will provide valuable input on designs aimed at enhancing the quality and reliability of Google's hardware products. The Platforms and Devices team you will be a part of focuses on Google's diverse computing software platforms across different environments (desktop, mobile, applications) and our first-party devices and services that integrate Google AI, software, and hardware to deliver innovative user experiences worldwide. Your responsibilities will include working with post-silicon validation teams to enhance and troubleshoot speed, Vmin, and yield-related issues. You will also collaborate with cross-functional teams involving circuit design, physical design, and sign-off methodology to drive innovation and improvements in circuit/Static Timing Analysis methodologies for advanced subsystems and System on a Chip (SoCs). Additionally, you will work with testchip teams on process nodes to construct, validate, and characterize custom Internet Protocols (IPs) and develop automation for circuit methodology, simulation, and analysis. Your role will be pivotal in ensuring the performance, reliability, and quality of Google's hardware products, thereby contributing to the seamless and efficient computing experiences for users globally.,