Senior Verification Engineer

Job Description

You are a passionate and meticulous Digital Verification Engineer with a keen interest in functional verification of High Speed interface IPs. With a dynamic personality and a strong eagerness to learn, you are driven to excel in Pre-silicon verification activities. Your understanding of digital design and HDL implementation sets you apart, and you thrive in environments where you can build and update verification plans and test cases . You are well-versed in scripting and automation using TCL, PERL, or Python , and possess excellent debug and diagnostic skills . Collaboration with digital designers is second nature to you, ensuring you achieve the desired coverage and performance in your projects. Your innovative mindset and commitment to excellence make you an invaluable asset to any verification team. What You'll Be Doing: Work on Functional Verification of High speed serial link PHY IPs for USBx, PCIex, Ethernet, Display & HDMI protocol standards. Study IP/design blocks/Firmware Specifications and build/update verification plans as well as the test cases. Build/update functional verification environments to execute the test plans. Implement checkers, assertions, random test generators, high level transactional models, and bus functional models (BFMs) as per the verification plan needs. Perform simulation, random and direct stimulus development, and coverage review. Work closely with digital designers for debug and achieve the desired coverage. The Impact You Will Have: Ensure the reliability and performance of High Speed interface IPs, critical to various advanced technologies. Contribute to the development of cutting-edge verification methodologies. Enhance the quality and efficiency of verification processes. Collaborate effectively with cross-functional teams to achieve project goals. Drive innovation in verification techniques, improving overall product quality. Support the creation of high-performance silicon chips that empower modern technology. What You'll Need: B.Tech/M.Tech with 3+ years of relevant experience. Understanding of functional verification flow with awareness of verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in scripting and automation using TCL, PERL, or Python. Strong debug and diagnostic skills. Experience in building and updating verification environments and test plans.