Senior Engineer Design Verification

Job Description

You will be working within DV team on verifying ORAN packet processing blocks using internal developed reference Python Model. Work on high speed SERDES interface verification such as PCIE but not limited to. Develop UVM testbench environment and execute verification cases to verify RTL design in bit true and cycle accurate. Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs. Develop and execute verification plans based on design specifications and collaboration with architects and designers. Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases. Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification. Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals. Work with FW team to convert DV sequence to FW drivers. Support emulation, FPGA, prototyping efforts. Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts. Job Requirements Masters and/or bachelors degree in engineering (or equivalent) in EC/ EE/ CS. 5 or more years of experience in ORAN protocol design verification using reference models. Hands-on experiences in integrating Python/C++ models to UVM environment and create Agents, Scoreboards components for network functional blocks. Experiences in Cadence vManager for DV metrics extraction and regression Good understanding of the complete verification life cycle (test plan, testbench through coverage closure). Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from scratch. Proficient in SystemVerilog, Verilog, UVM and C; and scripting languages like Python, Perl and Tcl/Shell. Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based Experiences in GIT, JIRA, MS office suites Benefits Competitive salary and stock options. Learning and development opportunities. Employer paid health Insurance. Earned, Casual, Sick parental leaves