You will be working within DV team on verifying ORAN packet processing blocks using internal developed reference Python Model. Work on high speed SERDES interface verification such as PCIE but not limited to. Develop UVM testbench environment and execute verification cases to verify RTL design in bit true and cycle accurate. Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs. Develop and execute verification plans based on design specifications and collaboration with architects and designers. Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases. Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification. Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals. Work with FW team to convert DV sequence to FW drivers. Support emulation, FPGA, prototyping efforts. Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts. Job Requirements Masters and/or bachelors degree in engineering (or equivalent) in EC/ EE/ CS. 5 or more years of experience in ORAN protocol design verification using reference models. Hands-on experiences in integrating Python/C++ models to UVM environment and create Agents, Scoreboards components for network functional blocks. Experiences in Cadence vManager for DV metrics extraction and regression Good understanding of the complete verification life cycle (test plan, testbench through coverage closure). Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from scratch. Proficient in SystemVerilog, Verilog, UVM and C; and scripting languages like Python, Perl and Tcl/Shell. Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based Experiences in GIT, JIRA, MS office suites Benefits Competitive salary and stock options. Learning and development opportunities. Employer paid health Insurance. Earned, Casual, Sick parental leaves

InnoPhase Inc., DBA GreenWave Radios , is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Headquartered in San Diego, California, GreenWave Radios has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global RD facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios continues to push the boundaries of radio technology and innovation. To learn more about GreenWave Radios and hear what our employees have to say, visit the GreenWave certification profile at GreatPlacetoWork.com or explore our Home - GreenWave Radios website. InnoPhase Inc., DBA GreenWave Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best - developing and implementing highly innovative SOC cellular radio integrated circuit products. Job Description InnoPhase Inc., DBA GreenWave Radios Bangalore is looking for a Tech Lead - SQA Automation to join our fast-paced and motivated team to drive excellence in our 5G products. This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning! Key Responsibilities Design, implement, and maintain automation test scripts for functional, regression, and performance testing. Develop and execute test automation strategies and plans that align with the project requirements and timelines. Build and maintain test automation frameworks using industry best practices and tools like Unittest, Pytest etc. Work closely with developers and business analysts to understand project requirements and to ensure test automation is integrated into the CI/CD pipeline. Lead, mentor, and provide technical guidance to a team of QA engineers, ensuring they follow best practices and efficient testing processes. Identify opportunities to improve testing processes and overall test automation effectiveness. Manage defects identified in automation, assist in root cause analysis, and follow through to ensure they are fixed in a timely manner. Take ownership of the automation test environment and provide technical leadership for the automation team. Research and recommend new automation tools, frameworks, and technologies to improve the efficiency of testing efforts. Lead the automation of performance testing using appropriate tools and methodologies. Job Requirements 10+ years experience required. B.E. EE/CS required, MS+ EE/CS preferred. Have technically lead and/or mentored a team of 2+ engineers for 2+ years. Strong coding skills in Python shell scripting and basic of C, C++ for development of test cases scripts. Have developed a complex test plan and managed execution of that test plan. Knowledge of ORAN, 5G or 4G Technology. Knowledge of experience with industry standard SQA tools, methodologies processes. Hands-on sophisticated CICD pipeline setup. Knowledge experience using Git Jira. Desirable Skills Prior System on a Chip (SoC) SQA experience. Good understanding of cellular wireless protocols (MAC/PHY), especially ORAN, LTE or 5G. Be able to work productively and independently. Team player with a strong sense of urgency to meet product needs on time. Benefits Competitive salary and stock options. Learning and development opportunities. Employer paid health Insurance. Earned, Casual, Sick parental leaves.

InnoPhase Inc., DBA GreenWave Radios , is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Headquartered in San Diego, California, GreenWave Radios has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global RD facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios continues to push the boundaries of radio technology and innovation. To learn more about GreenWave Radios and hear what our employees have to say, visit the GreenWave certification profile at GreatPlacetoWork.com or explore our Home - GreenWave Radios website. InnoPhase Inc., DBA GreenWave Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best - developing and implementing highly innovative SOC cellular radio integrated circuit products. Job Description InnoPhase Inc., DBA GreenWave Radios Bangalore is looking for a Senior Engineer - Design Verification to join our fast-paced and motivated team to drive excellence in our 5G products. This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning! Key Responsibilities You will be working within DV team on verifying HW wireless DSP blocks using internal developed reference MATLAB/Python Model. Develop UVM testbench environment and execute verification cases to verify RTL design in bit true and cycle accurate. Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs. Develop and execute verification plans based on design specifications and collaboration with architects and designers. Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases. Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification. Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals. Assist in emulation, FPGA, prototyping efforts. Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts. Job Requirements Masters and/or bachelors degree in engineering (or equivalent) in EC/ EE/ CS. 5 or more years of experience in DSP blocks(FFT, FIR, IIR, AGC, Interpolation/Decimation Filters, Up/Down Converter) design verification using reference models. Hands-on experiences in integrating MATLAB/Python models to UVM environment and create Agents, Scoreboards components for DSP blocks. Knowledge of wireless communication theories (SNR, IQ constellations, FFT, OFDM, MIMO) Experiences in Cadence vManager for DV metrics extraction and regression Good understanding of the complete verification life cycle (test plan, testbench through coverage closure). Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from the scratch. Proficient in SystemVerilog, Verilog, UVM and C; and scripting languages like Python, Perl and Tcl/Shell. Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based Experiences in GIT, JIRA, MS office suites Benefits Competitive salary and stock options. Learning and development opportunities. Employer paid health Insurance. Earned, Casual, Sick parental leaves.

InnoPhase Inc., DBA GreenWave Radios , is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Headquartered in San Diego, California, GreenWave Radios has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global RD facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios continues to push the boundaries of radio technology and innovation. To learn more about GreenWave Radios and hear what our employees have to say, visit the GreenWave certification profile at GreatPlacetoWork.com or explore our Home - GreenWave Radios website. InnoPhase Inc., DBA GreenWave Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best - developing and implementing highly innovative SOC cellular radio integrated circuit products. Job Description InnoPhase Inc., DBA GreenWave Radios Bangalore is looking for a Tech Lead - Design Verification to join our fast-paced and motivated team to drive excellence in our 5G products. This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning! Key Responsibilities You will be with team member as individual contributor and guide multi-core CPU and peripheral IP subsystem verification at block and SOC level Integrate 3rd party VIPs and develop testbench environment to perform verification of the design at IP/ Subsystem and SoC Level using SystemVerilog and UVM Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs. Develop and execute verification plans based on design specifications and collaboration with architects and designers. Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases. Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification. Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals. Assist in emulation, FPGA, prototyping efforts. Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts. Job Requirements Masters and/or Bachelor s degree in engineering (or equivalent) in EC/ EE/ CS. 10 or more years of experience in multi-core CPU peripheral IP(I2C, QSPI/OSPI, UART) design verification from test plan development to test case execution. Hands-on experiences using Cadence AMBA BFM and VIP with DV sequences and bare-metal C code. Experiences in Cadence vManager for DV metrics extraction and regression Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from the scratch. Proficient in SystemVerilog, Verilog/VHDL, UVM and C; and scripting languages like Python, Perl and Tcl/Shell. Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based test bench environments, writing SystemVerilog Assertions (SVAs), with embedded software design and testing. Strong knowledge about multiple testbench architectures, industry-standard interfaces/ protocols (AXI, AHB, APB, , PCIe, PIPE interface, Serdes, UART, SPI, I2C, QSPI, DMA etc). Experience in Cadence Design Tools/ Environments and exposure to Cadence VIPs/ UVCs is plus. Track record of successfully executing block or chip-level verification plans. Excellent communication and presentation skills, energetic and self-motivated. Work effectively with an off-site/ offshore design and verification teams across locations. Benefits Competitive salary and stock options. Learning and development opportunities. Employer paid health Insurance. Earned, Casual, Sick parental leaves.

InnoPhase Inc., DBA GreenWave Radios , is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Headquartered in San Diego, California, GreenWave Radios has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global RD facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios continues to push the boundaries of radio technology and innovation. To learn more about GreenWave Radios and hear what our employees have to say, visit the GreenWave certification profile at GreatPlacetoWork.com or explore our Home - GreenWave Radios website. InnoPhase Inc., DBA GreenWave Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best - developing and implementing highly innovative SOC cellular radio integrated circuit products. Job Description InnoPhase Inc., DBA GreenWave Radios Bangalore is looking for a Tech Lead - Design Verification to join our fast-paced and motivated team to drive excellence in our 5G products. This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning! Key Responsibilities You will be working within DV team on verifying HW wireless DSP blocks using internal developed reference MATLAB/Python Model. Develop UVM testbench environment and execute verification cases to verify RTL design in bit true and cycle accurate. Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs. Develop and execute verification plans based on design specifications and collaboration with architects and designers. Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases. Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification. Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals. Assist in emulation, FPGA, prototyping efforts. Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts. Job Requirements Masters and/or bachelors degree in engineering (or equivalent) in EC/ EE/ CS. 10 or more years of experience in DSP Blocks (FFT, FIR, IIR, AGC, Interpolation /Decimation Filter,Up/Down Converter) design verification using reference models. Hands-on experiences in integrating MATLAB/Python models to UVM environment and create Agents, Scoreboards components for DSP blocks. Knowledge of wireless communication theories (SNR, IQ constellations, FFT, OFDM, MIMO) Experiences in Cadence vManager for DV metrics extraction and regression. Good understanding of the complete verification life cycle (test plan, testbench through coverage closure). Proficient in SystemVerilog, Verilog, UVM and C; and scripting languages like Python, Perl and Tcl/Shell. Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based. Experiences in GIT, JIRA, MS office suites. Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from the scratch. Benefits Competitive salary and stock options. Learning and development opportunities. Employer paid health Insurance. Earned, Casual, Sick parental leaves.