Master s and/or bachelor s degree in engineering (or equivalent) in EC/ EE/ CS. 10 or more years of relevant experience across multiple verification environments for IPs, Sub-systems, and SoCs. Proficient in SystemVerilog, UVM, Verilog/VHDL; scripting languages (Python, Perl, Tcl/Shell etc.) and experience with Bare-Metal C Program. Expertise in developing UVM testbench environment and components (Monitor, Scoreboard, Driver, Agent etc), SystemVerilog Assertions (SVAs) and Functional Coverage. Proficient with ARM Processors (Cortex) based SoC verification, multi-processor Cache Coherency and Memory/DMA controllers. Strong working knowledge on bus/ interconnect protocols like AMBA AXI/AHB/APB, PCIe, USB, Ethernet etc. Experience with industry-standard interfaces (PIPE, SerDes etc.) and peripheral protocols QSPI, SPI, UART, I2C etc. Hands-on experience with integration of VIPs/UVCs (Cadence/ Synopsys) and C-reference models into multiple UVM testbench environments. Experience in Cadence Design, Simulation & Debug Tools/ Environments and vManager for DV metrics extraction and regression. Track record of successfully executing block or chip-level verification strategy & plans. Excellent communication and presentation skills, energetic and self-motivated. Work effectively with an off-site/ offshore design and verification teams across locations.
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