Senior DFT Lead

You are an experienced Design for Testability (DFT) Engineer who will be responsible for leading and defining the overall DFT strategy for critical ASIC and SoC projects at HCL Tech. Your expertise in DFT methodologies is crucial for driving the implementation of robust test strategies to ensure the manufacturability and high-quality testing of next-generation integrated circuits. In this senior-level role, you will collaborate with design and verification teams to seamlessly integrate DFT techniques throughout the design flow. Your responsibilities include developing and implementing advanced DFT methodologies such as scan insertion, ATPG, Boundary Scan, and Design for X to achieve exceptional test coverage and fault detection rates. You will also champion best practices for DFT, participate in design reviews, mentor junior engineers, and analyze test results to identify and address potential design issues. To qualify for this position, you should hold a Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with a minimum of 10+ years of experience in DFT for complex ASICs and SoCs. Your proven track record of successfully leading DFT strategies for high-volume production and in-depth knowledge of advanced DFT concepts are essential. Additionally, expertise in industry-standard DFT tools and scripting languages for automation, as well as a strong understanding of digital design principles and manufacturing test processes, will be beneficial. Joining HCL Tech as a DFT Engineer offers competitive salary and benefits, the opportunity to lead cutting-edge DFT strategies, a dynamic work environment with professional growth opportunities, and recognition for outstanding contributions. If you are a highly accomplished DFT Engineer looking to make a significant impact in the field of integrated circuits, this role is perfect for you.,