RTL/IP Design

As a RTL/IP Design Engineer at Sykatiya Technologies, you will be an integral part of our highly talented team that contributes to customer projects with Technical Ability and the right Attitude. With a focus on Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs, you will have the opportunity to showcase your skills and expertise. Key Responsibilities: - Possess 5+ years of experience in digital ASIC front-end design - Demonstrate a strong understanding of design flow including RTL (VHDL, Verilog, and/or SystemVerilog) - Utilize simulation tools such as Questa or Xcelium and have experience in logic synthesis (e.g. Synopsys DC) - Hands-on experience with embedded microcontrollers and AMBA bus systems Qualifications Required: - Bachelor's degree in science/engineering - Fluency in English language Join us in Bangalore and be a part of a dynamic team where your contributions will make a difference in the success of our projects.,