2.0 - 6.0 years

0 Lacs

karnataka

On-site

You have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. You possess 3 years of experience in architecture, hardware, digital design, and software design, along with 2 years of experience in Verilog/SystemVerilog. Your experience includes knowledge in computer architecture and digital design or Internet Protocol (IP) integration such as Peripheral Component Interconnect Express (PCIe) and Double Data Rate (DDR) memory. Ideally, you hold a Master's degree in Electrical Engineering, Computer Science, or a related field and have 4 years of experience working on Field Programmable Gate Array (FPGA) platforms or Emulation platforms with Internet Protocols (IPs) like PCIe, DDR memory, Gigabit Ethernet, and Flash. You also have experience in developing architectures for Machine Learning Accelerators and in writing or debugging Verilog/Register-Transfer Level (RTL) code for ASIC/FPGA designs, with waveform debug skills and knowledge of chip design flows. As part of this role, you will contribute to shaping the future of AI/ML hardware acceleration, particularly focusing on TPU (Tensor Processing Unit) technology that drives Google's demanding AI/ML applications. You will collaborate with a diverse team to develop custom silicon solutions that power Google's TPU, innovating products enjoyed by users worldwide. Your responsibilities will involve verifying complex digital designs, especially TPU architecture integration within AI/ML-driven systems. Your tasks will include integrating hardware and software stacks for pre-silicon validation of Google Cloud Tensor Processing Unit (TPU) projects using emulation platforms, creating custom test cases and tools, and ensuring the quality of silicon bring-up, validation, and characterization programs. Additionally, you will work on debugging issues, collaborating with various teams, and contributing to the development of tools, validation firmware, and testing infrastructure for Google Cloud data center systems. Overall, your role will focus on enabling chip features through firmware and driver stack, validating hardware and software designs, designing ASIC models for Emulation/FPGA Prototypes, optimizing RTL transformations, and improving hardware modeling accuracy. You will play a key role in driving debug discussions, coordinating hardware and software deliveries, and benchmarking performance to ensure efficient operations of Google's systems.,

Posted 4 days ago

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