5.0 - 10.0 years

80 - 85 Lacs

bengaluru

Work from Office

Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design.Set up and configure STA tools (e.g., Cadence Encounter, Synopsys PrimeTime) for the analysis, including library characterization, delay models, and clock definitions. Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations). Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metasta...

Posted 3 weeks ago

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Synthesis + STA Engineer (SI80FF RM 3488) Sourceright Technologies

8.0 - 13.0 years

6 - 8 Lacs

bengaluru, karnataka, india

On-site

Strong understanding of timing closure for multi-clock, high-frequency timing, congestion, crosstalk, and area-sensitive designs. Collaborate with RTL designers for constraint development and cleanup. Proficient in Synopsys/Cadence tools with hands-on experience in advance features of Design compiler and PrimeTime SI. Deep expertise in low-power design (UPF/CPF), clock gating, logic optimization, and integration of high-speed interfaces like DDR and PCIe Provide technical leadership to successful tape outs at advanced technology nodes (7nm, 5nm and 3nm). Good scripting, communication and debugging skills.

Posted 2 months ago

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