Synthesis + STA Engineer (SI80FF RM 3488) Sourceright Technologies

8.0 - 13.0 years

6 - 8 Lacs

bengaluru, karnataka, india

On-site

Strong understanding of timing closure for multi-clock, high-frequency timing, congestion, crosstalk, and area-sensitive designs. Collaborate with RTL designers for constraint development and cleanup. Proficient in Synopsys/Cadence tools with hands-on experience in advance features of Design compiler and PrimeTime SI. Deep expertise in low-power design (UPF/CPF), clock gating, logic optimization, and integration of high-speed interfaces like DDR and PCIe Provide technical leadership to successful tape outs at advanced technology nodes (7nm, 5nm and 3nm). Good scripting, communication and debugging skills.

Posted 2 weeks ago

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