Physical Design (STA Lead)

As a Senior Clocking Engineer with over 10 years of experience, you will play a crucial role in leading the development and execution of clocking strategies for high-performance Integrated Circuits (ICs). Your responsibilities will include defining and managing timing constraints throughout the design flow to ensure accurate timing analysis. You will be expected to perform advanced Static Timing Analysis (STA) using industry-standard tools, identifying potential timing violations and bottlenecks. In this role, you will develop and maintain robust clock tree synthesis (CTS) methodologies for optimal clock distribution and skew control. You will also drive the creation and execution of a comprehensive clock domain crossing (CDC) verification plan. Collaboration with design engineers, layout engineers, and other physical design teams will be essential to address timing closure challenges effectively. As a mentor, you will coach and guide junior engineers, helping them grow and develop expertise in clocking, constraints, and STA practices. Staying updated with the latest advancements in clocking methodologies, timing analysis tools, and industry best practices will be a key part of your role. Additionally, you will lead the evaluation and implementation of new tools and methodologies to enhance timing closure efficiency. Your role will also involve developing and maintaining comprehensive documentation for clocking, constraints, and STA practices within the team. Your expertise and leadership in clocking strategies will be instrumental in ensuring the successful implementation of timing solutions for high-performance ICs.,