4.0 - 6.0 years

0 Lacs

coimbatore, tamil nadu, india

On-site

Job Title: Physical Design Engineer Experience: 4+ Years Location: Coimbatore Employment Type: Full?time Required Qualifications Bachelor's or Master's degree in Electronics/Electrical/Computer Engineering or related field. 4+ years of hands?on experience in ASIC/SoC Physical Design . Strong understanding of physical design flows (RTL2GDSII). Experience with EDA tools such as Synopsys , Cadence , Mentor e.g., IC Compiler, Innovus, PrimeTime, Tempus, Hercules, etc. Proficiency in STA, timing closure techniques, clocking strategies, congestion analysis. Good scripting skills in Tcl , Perl , Python , or Shell . Knowledge of power analysis, floorplanning, ECO flow, clock tree synthesis, and rout...

Posted 4 days ago

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Physical Design (STA Lead) HCLTech

10.0 - 14.0 years

0 Lacs

karnataka

On-site

As an experienced candidate with over 10 years of experience, you will be responsible for leading the development and implementation of comprehensive clocking strategies for high-performance ICs. Your key responsibilities will include: - Defining and managing timing constraints throughout the design flow to ensure accurate and consistent timing analysis. - Performing advanced Static Timing Analysis (STA) using industry-standard tools to identify potential timing violations and bottlenecks. - Developing and maintaining robust clock tree synthesis (CTS) methodologies for optimal clock distribution and skew control. - Driving the creation and execution of a comprehensive clock domain crossing (...

Posted 2 months ago

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Physical Design (STA Lead) HCLTech

10.0 - 14.0 years

0 Lacs

karnataka

On-site

As a Senior Clocking Engineer with over 10 years of experience, you will play a crucial role in leading the development and execution of clocking strategies for high-performance Integrated Circuits (ICs). Your responsibilities will include defining and managing timing constraints throughout the design flow to ensure accurate timing analysis. You will be expected to perform advanced Static Timing Analysis (STA) using industry-standard tools, identifying potential timing violations and bottlenecks. In this role, you will develop and maintain robust clock tree synthesis (CTS) methodologies for optimal clock distribution and skew control. You will also drive the creation and execution of a compr...

Posted 4 months ago

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