Lead Engineer - Functional Formal Verification

As a Formal Verification Engineer at our Global Technology organization, you will be responsible for leading formal verification activities for single or multiple design blocks and IPs. This includes developing and executing formal verification strategies and test plans to ensure the correctness of designs. Your role will involve creating detailed formal verification plans, identifying design properties, and collaborating with design teams to enhance micro-architectures. You will play a key role in crafting innovative solutions to verify complex design architectures by developing reusable formal models and verification code bases. Additionally, you will mentor junior team members and provide technical leadership in formal verification methodologies, including training on industry-standard tools and techniques. Collaboration with cross-functional teams, such as design and verification, will be essential to ensure the seamless integration of formal verification into the overall verification flow. The ideal candidate for this position should possess expertise in formal verification techniques and methodologies, a strong command of System Verilog and Universal Verification Methodology (UVM), and hands-on experience with tools like Jasper or VC Formal (Synopsys). You should have the ability to develop reusable verification models and formal strategies, along with strong debugging, problem-solving, and team collaboration skills. Experience in mentoring engineers and driving technical leadership will be beneficial in this role. To qualify for this position, you should hold a Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field. Join us in our dynamic team environment where you can contribute to cutting-edge technology developments and drive innovation in formal verification processes.,