IP/RTL Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiencesfrom AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challengesstriving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

MTS SILICON DESIGN ENGINEER

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The Role

The focus of this role is to microarchitect , design and deliver data fabric IP RTL . These include new and existing features and components for AMD's data fabric IP , working in close coordination with verification to ensure design quality.??

THE PERSON:

?You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.?

KEY RESPONSIBILITIES:

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• Digital design implementation and micro-architecture of components of the Infinity Data Fabric
• Micro-architecture and RTL coding in Verilog/SystemVerilog of Data fabric components and its features as the fabric scales for server, data centre application systems.
• Design of Power Management flows and architecture for the fabric
• Collaborate with architectss to understand the new features to be implemente
• Knowledge of cache coherency and/or fabric /NOC design is a plus
• Leaf level cache designing
• Collaborating with verification and integration teams to resolve inter IP integration issues
• Design flow quality checks - Lint, CDC, RDC and others
• Timing closure - timing constraints, synthesis, logic-depth reduction
• Design area optimizations
• Low power design techniques, UPF included
  

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PREFERRED EXPERIENCE:

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