IP Design Verification Engineer

Creates quality Pre-Silicon Validation collaterals using UVM System Verilog/SystemC and integrates it with the emulation/FPGA model. Tests and debugs the emulation/FPGA model and collaterals for validation readiness.

Defines and develops new capabilities and HW/SW tools to enable acceleration of RTL and improve emulation/ FPGA model usability for pre-silicon and post-silicon functional and performance validation as well as SW development/validation.

Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. Interfaces with and provides guidance to Pre-Silicon Validation teams for optimizing pre-silicon validation environments, test suites and methodologies for emulation efficiency.

Develops and applies automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization.

Job Experience:

Technical experience in verification of RTL-based digital systems with very good understating of various system level flows.

Experience leading development of verification architecture based on evolving requirement from IP/SOC customers.

Experience with RTL design, Verilog and simulation, debug tools such as Verdi, System Verilog/ SystemC based verification techniques.

Experience in debugging and isolation techniques including writing checkers, monitors, assertions and necessary DPI interfaces for co-emulation environments.

Experience in SW Programming/scripting and debug such as C, C++, Perl, Python.

Work experience creating a self-checking emulation/simulation test bench.

Highly proficient in UVM techniques for verification.

Hands-on experience of emulation and simulation BFM based verification.

Good understanding of architectural design documents(micro-architecture documents, integration documents).

Preferably good understanding of emulation/simulation platform with major vendors (Synopsys, cadence ).

Protocol knowledge : PCIE, CXL, UCIe, CHI, DDR

Good understanding of CPU architecture (Intel/AMD/ Arm/GPU).

Highly proficient with coherent, non-coherent and concurrent traffic validation.

Experience with emulation based systems such as Synopsys ZeBu, Cadence Palladium or Mentor Graphic Veloce Experience in building emulation based models for large scale designs is a plus.

Job Responsibilities:

Work closely with peers in architecture, design and verification teams

Should be able to review the IP teams requirements, come up with verification plan, test plan, micro-arch, identify scenarios and design intent and develop verification strategies which can ensure defect free IP's.

Maintain generic emulation-based verification environment and regression setups for various IP'sLeads activities driving the development of various stimulus to support the emulation based verification of various IP's.

Develop and maintain UVM environments for IP interfacesWork in cross-functional teams to deliver bug free features in a timely manner

Qualifications
This position requires meeting the below minimum qualifications to be initially considered. Preferred qualifications are in addition to the minimum requirements and are considered a major plus.

Minimum Qualifications:

Must have a Bachelor's degree with 10+ year experience or Master's degree in Electronics and Computer Engineering with relevant experience of at least 7+ years.