Formal Verification Engineer

As a Formal Verification Engineer at our company, you will play a crucial role in ensuring the functional correctness of complex IP and SoC designs by developing and executing formal verification strategies. Your responsibilities will include: - Defining and implementing formal verification strategies and plans. - Developing formal properties and assertions for critical design blocks. - Applying formal techniques such as property checking, sequential equivalence checking, and formal coverage. - Analyzing formal results, identifying unreachable or vacuous properties, and refining models. - Collaborating closely with RTL designers, DV engineers, and architects. - Integrating formal into the overall verification methodology and sign-off. - Documenting and presenting formal verification methodologies, assumptions, and results. Qualifications required for this role include: - 4+ years of experience in formal verification using industry tools (e.g., JasperGold, VC Formal, Questa Formal, OneSpin). - Strong knowledge of SystemVerilog Assertions (SVA) and formal property specification. - Solid understanding of digital design concepts and RTL coding in Verilog/SystemVerilog. - Familiarity with formal coverage metrics and convergence techniques. - Experience in debugging complex design bugs using formal tools. - Ability to abstract and model designs or protocols at different levels. Desirable skills that would be a plus for this role include: - Familiarity with safety-critical designs (ISO 26262, DO-254). - Knowledge of common protocols such as AXI, AHB, PCIe, Ethernet, etc. - Exposure to sequential equivalence checking and abstraction modeling. - Understanding of simulation-based verification and integration with formal. - Proficiency in scripting (Python, Perl, or TCL) for automation. If you are interested in this opportunity, please share your CV to sharmila.b@acldigital.com.,