FCV Verification Engineer

As a Verification Engineer at this company, you will be responsible for demonstrating good verification skills in Verilog and System Verilog. You should have a strong understanding of digital design fundamentals and possess knowledge of UVM methodology. Additionally, you must be proficient in scripting languages such as Perl and Make, and showcase excellent problem-solving and debugging skills. The company follows a structured UVM methodology for verification, and you will be expected to contribute to projects by leveraging your skills in UVM, Verilog, System Verilog, Perl, and Make. If you are interested in applying for this position, kindly submit your details and updated resume to hr@incise.in, including your current CTC, expected CTC, and notice period. Our team will reach out to you for further discussions.,