DFT Sr Engineer - MBSIT, ATPG - STA constraints timing

The Role:

• As a key member of the S3 SoC DFT Team, the successful candidate will play a significant role in ensuring the quality of next generation AMD SoCs through structural DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques.

Key Responsibilities:

• Develop full chip DFT Synthesis and DFT STA constraints.

• STA constraint development of DFT modes (ScanShift, Atspeed, MBIST)

• Set up DFT timing constraints, defining the overall SOC Test STA methodology.

• Working with the Design team to clean-up all the DFT related constraint issues

• Closely work with physical design team to generate and validate timing constraints

• Developing, improving and maintaining automation scripts as necessary

Preferred Experience:

• Experience in DFT architecture for complex chips

• Exposure to Static timing analysis & Timing closure is required.

• Proven experience in DFT constraints handling, Block and Top-level test mode Static timing analysis (STA).

• Experience in SOC timing closure in DFT modes and sign-off

• Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required.

• Excellent hands-on debug skills and scripting skills are critical.

Qualification:

• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering with 8 to 10 years of DFT Experience

• #LI-RR1
  
• #L!-Hybrid