Design Verification Engineer (Pre-Silicon, SoC/IP DV)

Overview:

globally recognized product engineering organization

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Job Details:

Requirement:

Job type:

Location:

Experience:

Notice period:

Required Skills:

• 8+ years of design verification experience.
• Must have experience with Verilog and popular EDA simulation,

  System Verilog assertions and testbench methodologies

• Responsible for verification of various

  IP's and/or SoC

• Must have experience in developing complex test bench in System Verilog using

  UVM methodology

• Hands-on experience in

  AMBA protocol, Bluetooth MAC, Wifi 802.11 MAC layer protocol

• Experience in

  Low Power Simulation/UPF setup, debug low power simulation failures.

• Exposure to scripting languages like Perl, Unix shell or similar languages.

Thanks and Regards,

iitjobs, Inc.

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