9 Ddr5 Jobs

Project description This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions. Responsibilities Drive the development of cutting-edge memory-related firmware projects, contributing to the creation of innovative solutions Collaborate with a highly regarded team to bring innovation to memory-related firmware, ensuring solutions are at the forefront of industry advancements Tackle complex challenges by employing strong problem-solving skills, enhancing firmware to meet evolving performance and reliability standards Skills Must have 5-10 years' experience. Strong with C language programming Working knowledge of git/gerrit Experience with memory recognition and configuration code Experience with hardware debug tools Good problem-solving, analysis and debugging skills Good understanding of DDR4, DDR5, NVDIMM Good understanding of different DIMM types (UDIMM/SODIMM/RDIMM/LRDIMM/LPDDR) Good understanding of UMC features like ECC, SME, SEV, RAS etc Nice to have Understanding different vendor implementations and memory timing differences is a big plus Notice Period: Any

Hot Vacancy Design Verification Engineer (5–10 Years) Location: Bangalore Experience: 5 to 10 Years Industry: Semiconductors / VLSI / ASIC Employment Type: Full Time Joining: Immediate to 30 days preferred Job Description: We are actively hiring skilled and passionate Design Verification Engineers with 5–10 years of experience for multiple cutting-edge SoC/ASIC. Roles and Responsibilities: Develop test plans , testbenches , and testcases using System Verilog and UVM . Own block-level and/or SoC-level verification and drive coverage closure . Verify protocols and interfaces such as AXI, AHB, PCIe, LPDDR5, UCIe, I3C, CXL , etc. Perform assertion-based verification (SVA) and support gate-level simulations (GLS) . Collaborate with cross-functional teams including RTL. Desired Candidate Profile: 5–10 years of hands-on experience in ASIC/SoC functional verification . Strong in System Verilog, UVM . B.E./B.Tech or M.E./M.Tech in ECE/EEE/CSE or related fields. Why Join Us? Work on next-gen chip designs with global teams. Opportunity to work on latest protocols and IPs . Interested Candidates share your resumes to priya@maxvytech.com and hr@maxvytech.com

We are seeking a highly skilled and motivated Firmware Software Development Engineer (Memory Management) to join the offshore development teams of our group companies You will work with the rapidly expanding team which focuses on the research and development of embedded products You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Bangalore, Belgrade, Penang, New York Desired Profile Engineers with expertise in firmware development related to memory recognition and configuration code Expertise in embedded C programming Expertise in using hardware debug tools Good problem solving, analysis and debugging skills Good understanding of DDR4, DDR5, NVDIMM Good understanding of different DIMM types (UDIMM / SODIMM / RDIMM / LRDIMM / LPDDR) Good understanding of UMC features like ECC, SME, SEV, RAS etc Understanding of different vendor implementations and memory timing difference is a big plus Knowledge of platform BIOS and UEFI / Coreboot is a big plus Scripting knowledge is a plus Rewards And Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process. NOTE : Preferred resources holding valid regional work permits only

IP/RTL Design Engineer for ARM CMN Fabric and Neoverse Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore IP/RTL Design Engineer for ARM CMN Fabric and Neoverse Position Overview Seeking an IP/RTL Design Engineer with 10+ years of experience to design IP/RTL for ARM Neoverse-based SoCs, focusing on CMN fabric, using Socrates for configuration, targeting AI/HPC datacenter applications. Key Responsibilities Design IP blocks for ARM Neoverse SoCs, integrating CMN fabric (e.g., CMN-700/S3) for cache coherence and interconnect. Develop Verilog/SystemVerilog RTL for high-performance, low-latency designs. Configure CMN topologies using Arm Socrates for optimized performance and scalability. Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects. Optimize designs for bandwidth, latency, and power in AI/HPC workloads. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS/PhD in Electronics/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, 5+ years with ARM Neoverse and CMN fabrics (e.g., CMN-600/700/S3). Skills: Expert in Verilog/SystemVerilog RTL design. Deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects. Deep understanding in system architecture, coherence and cache Experience with Arm Socrates for CMN configuration. Proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols. Familiarity with synthesis and timing tools (e.g., Synopsys Design Compiler). Experience with AI/HPC or datacenter SoC design. Knowledge of DDR5, HBM3, or chiplet-based architectures. Familiarity with UALink or Ultra Ethernet. Strong problem-solving and collaboration skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Memory ControllerVerification- Principal Location: Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Bangalore A US based well-funded product-based startup looking for Highly talented Verification Engineers for the following roles. Memory Controller - Principal / Senior Staff Verification Engineers: looking for experienced and talented professional for DDR Memory Controller Verification. Minimum Qualifications: BE/BTech in Electrical/Computer engineering with 10+ years of experience or ME/MTech in Electrical/Computer engineering with 8+ years of experience Should have hands on experience in System Verilog, UVM/OVM and Object-Oriented Programming Proven track record in DDR5/LPDDR5X/LPDDR6/HBM4 IP verification from environment and tests development to validation closure Work closely with RTL designers and SOC team to scope out integration and verification requirements Proficiency in bus protocols AXI/AHB Integration and verification of complex System IP features. Proficiency in scripting languages like Perl, Python etc. Strong communication, collaboration, and interpersonal skills Strong analytical and problem-solving skills Preferred Qualifications: Experience in Memory controller, DDR4/5, LPDDR4/5, HBM memory protocols Knowledge of Fabric/Network on chips, Cache Coherency Experience in GLS is added advantage. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Memory Controller - Staff Verification Engineers Location : Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for Highly talented Verification Engineers for the following roles. Memory Controller - Staff Verification Engineers: looking for experienced and talented professional for DDR Memory Controller Verification. Minimum Qualifications: BE/BTech in Electrical/Computer engineering with 6-8+ years of experience Should have hands on experience in System Verilog, UVM/OVM and Object-Oriented Programming Proven track record in DDR5/LPDDR5X/LPDDR6/HBM4 IP verification from environment and tests development to validation closure Work closely with RTL designers and SOC team to scope out integration and verification requirements Proficiency in bus protocols AXI/AHB Integration and verification of complex System IP features. Proficiency in scripting languages like Perl, Python etc. Strong communication, collaboration, and interpersonal skills Strong analytical and problem-solving skills Preferred Qualifications: Experience in Memory controller, DDR4/5, LPDDR4/5, HBM memory protocols Knowledge of Fabric/Network on chips, Cache Coherency Experience in GLS is added advantage. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

In this role you will work on SoC/Sub-system level Emulation model development and design bring up on Zebu/Veloce HW platforms. Additionally, you will work closely with design, verification, validation, and SW teams to implement emulation testbench (XTORs, Speed Adaptors) and features required to develop content on emulation models. You would develop tests to qualify models. Key Skills 8-15 years of experience on SoC/Sub-system Emulation of multi-million gate and complex design with multiple clocks and power domains Experience in microcontroller architecture, Cores ARM A/M series, Interconnect (NIC, FlexNoC), Protocols like AHB, AXI, Memory (Flash, SRAM, DDR4/5), and memory controllers Experience in automotive protocols like LIN, CAN, high-speed protocols like PCIe, Ethernet, USB etc. would be an advantage Emulation model creation from RTL/Netlist Experienced in Zebu/Veloce emulation platforms Create and execute test plans targeting emulation model qualification Experience with Speed Bridge Integration and perform real-time testing would be a plus Experience in integrating Acceleration VIPs/XTORs and perform co-emulation Scripting and Automation to continuously improve operational efficiency.

Principal Design Verification Engineer (India) Bangalore (Hybrid ) / Hyderabad (Hybrid ) Principal Design Verification Engineer (India) India Company Background We areon a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, We are unleashing the revolution in next-gen computing fabrics. Summary Join an ambitious, experienced team of silicon and distributed systems experts as a design verification engineer. You have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and to help solve key infrastructure challenges facing our customers. We are looking for talented, motivated candidates with experience designing and verifying large-scale networking and computing chips, and who are looking to grow in a fast paced, dynamic startup environment. We seek experienced verification engineers who can contribute across the full lifecycle of complex chip development, from microarchitecture definition to DV infrastructure and test development, to post-silicon testing. Roles and Responsibilities Collaborate with world-class distributed systems hardware and software architects to transform product vision and behavioral specifications into efficient, comprehensive block-level and top-level tests which achieve outstanding coverage. Incorporate state-of-the art verification techniques to efficiently tackle the demanding scale and performance requirements of a functionally complex device. Define and implement infrastructure for effective HW/SW co-simulation. Execute on a verification strategy which ensures that the prototype meets both the device level specifications as well as the system-level requirements. The ideal candidate should have the versatility to build infrastructure and tests that can be leveraged across both ASIC and FPGA platforms. Skills/Qualifications Proven industry experience and successful track record in verifying chip- and block-level RTL designs for high-performance networking or computing chips, such as Network Interface Controllers, Smart-NICs, DPUs, accelerators, and/or switches in advanced silicon geometries. DDR5 DDR6 Deep experience with full chip verification and infrastructure development. Strong current knowledge of UVM constructs, components, and practices. Expert knowledge of SystemVerilog, as well as Python or other scripting languages. Experience with C/C++ and general software engineering principles is highly desirable. Minimum BSEE/CE + 12-17years or MSEE/CE + 12-15 years experience. Proven track record of design execution and quality on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon Staff Design Verification Engineer Job Description In this role you will be responsible Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it functions to the standards of being launch ready for the end Product. Role And Responsibilities Partner with Architects and RTL Design team to grasp high-level system requirements and specifications. Formulate comprehensive test and coverage plans to match the Architecture and micro-architecture. Define and implement a verification methodology that supports scalability and portability across various environments spanning including post-silicon. Develop the verification environment and reusable bus functional models, stimulus, checkers, assertions, trackers, and coverage metrics. Create verification plans and develop testbenches tailored to assigned IP/Subsystem or functional domain. Execute verification plans, including tasks such as design bring-up, setting up the DV environment, running regressions for feature validation, and debugging test failures. Support post-Si bring-up and debug activities. Track and communicate progress in the DV process by using key metrics like bug tracking and coverage reports. Requirements Bachelors or Masters degree in Electrical or Computer Engineering/Science Strong Architecture domain knowledge in x86/ARM CPU, or Memory, Coherency, Virtualization or Performance areas. Must have strong expertise with SV/UVM methodology and/or C/C++ based verification with 7yrs+ hands-on experience in IP/sub-system and/or SoC level verification Hands on experience and expertise with industry standard verification tools for simulation and debug (Questa/VCS, Visualizer) Experience using random stimulus along with functional coverage and assertion based verification methodologies a must. Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation. Preferred Qualifications: Experience in development of UVM based verification environments from scratch. Hands on expertise and protocol knowledge in any of: APB/AXI/CHI, JTAG/I3C/SPI, , DDR5/LPDDR5/HBM, PCIE/CXL/UCIE/Ethernet compliance testing