Job
Description
You will be part of a Physical Design / Timing Closure team for projects with GHz frequency range and cutting-edge technologies. Your primary responsibility will involve developing timing constraints for full chip or block level designs. Additionally, you will be accountable for STA signoff for complex multi-clock, multi-voltage SoCs. Your role will entail Synthesis, Timing Analysis (STA), and Clock Tree Synthesis (CTS) at Full Chip or block level, particularly focusing on Lower tech nodes below 14nm. To excel in this role, you should hold a B. Tech. / M. Tech. degree with 4-10 years of experience in Synthesis and STA. Your expertise should extend to the synthesis of complex SoCs at block/top levels and crafting timing constraints for intricate designs featuring multiple clocks and voltage domains. Previous experience in pre and post-layout timing analysis and proficiently resolving associated issues is crucial. Moreover, you should possess hands-on experience in post-layout timing closure for multiple tape outs, encompassing timing Engineering Change Orders (ECOs) and STA signoff. Demonstrated proficiency in developing I/O constraints for various Industry standard protocols such as DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Display, among others, is highly desirable. Your technical skills should extend to working on technology nodes like 28nm, 20nm, 14nm, and 10nm. A good understanding of Electronic Design Automation (EDA) tools like RC, DC, PT, and PTSI is essential. Furthermore, your role may involve formal verification of RTL-to-netlist and netlist-to-netlist with Design-for-Testability (DFT) constraints. A solid grasp of VLSI processes, device characteristics, deep submicron parasitic effects, crosstalk effects, etc., is expected. Proficiency in TCL and Perl scripting will be advantageous to perform the tasks effectively. Overall, as an STA Engineer specializing in Timing Closure and Synthesis, you will play a crucial role in ensuring the successful completion of projects involving advanced technologies and stringent timing requirements.,
