3.0 - 7.0 years

7 - 11 Lacs

bengaluru

Work from Office

About The Role Your Role As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will collaborate closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process corners. In this role, you will: Own full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages Develop and validate timing constraints (SDC) for blocks, partitions, and full-chip designs Perform timing analysis using industry-standard tools (e.g., PrimeTime, Tempus) Collaborate with design and architecture teams to define timi...

Posted 1 day ago

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Associate II - VLSI-STA_SV UST

4.0 - 10.0 years

0 Lacs

karnataka

On-site

You will be part of a Physical Design / Timing Closure team for projects with GHz frequency range and cutting-edge technologies. Your primary responsibility will involve developing timing constraints for full chip or block level designs. Additionally, you will be accountable for STA signoff for complex multi-clock, multi-voltage SoCs. Your role will entail Synthesis, Timing Analysis (STA), and Clock Tree Synthesis (CTS) at Full Chip or block level, particularly focusing on Lower tech nodes below 14nm. To excel in this role, you should hold a B. Tech. / M. Tech. degree with 4-10 years of experience in Synthesis and STA. Your expertise should extend to the synthesis of complex SoCs at block/to...

Posted 5 months ago

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