ASIC RTL Design

Job Description

Seeking a skilled RTL Design Lead/Manager (ASIC) : - 6-20 years experience in VLSI RTL IP/Subsystem design - Expertise in SoC Clock, Power IP/Subsystem, BUS/Subsystem, and more . Profound grasp of Digital design principles, especially AMBA SoC BUS protocols like APB, AXI, and AHB. . Crafting micro-architecture and detailed design docs for SoC Subsystem, focusing on performance, power, and area requirements. . Exceptional debugging skills and extensive experience with DV tools like Verdi, NCSIM. . Preferable experience in SOC Integration at Top Level, Block Level, or Subsystem level. . Collaborating with DV team for verification coverage enhancement and GLS closure with DV, PD, and Modeling team. . Knowledge in CDC, Linting, UPF, DFT, and Multi-Voltage-Rule-Check analysis. . Familiarity with ASIC Synthesis, static timing reports analysis, Formal checking, etc. . Defining constraints, ensuring critical high-speed path timing closure with back end teams. Exposure to quality processes in SoC design and verification is a plus. Thrive in a fast-paced consumer SoC design environment with stringent deadlines and quality benchmarks. CV submission: pathan.khan@wipro.com