Were looking for a skilled Analog/RF ASIC Design Engineer to join our team. This role is ideal for someone with a strong background in RFIC or analog IC design , and hands-on experience with Cadence Virtuoso . Preferred candidate profile 8+ years of experience in Analog or RF IC design . Strong hands-on skills with Cadence Virtuoso and analog simulation tools. Experience with PLL or other high-frequency analog circuits. Solid understanding of analog design fundamentals (noise, matching, stability, etc.). Bachelors or Master’s degree in Electrical or Electronics Engineering.

Extensive Experience In SAP APO Deployment Optimizer. Some Experience With SAP IBP Will Be A Plus. Show more Show less