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Analog Physical Design Engineer-Cadence, chip tape, nodes - Hyderabad

5 - 10 years

30 - 45 Lacs

Hyderabad

Posted:1 day ago| Platform: Naukri logo

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Skills Required

chip tape Analog Design Cadence higher nodes digital blocks

Work Mode

Work from Office

Job Type

Full Time

Job Description

Role: Analog Physical Design Engineer Exp: 5+ years Work location: Hyderabad ODC projects based in Hyderabad. Digital blocks in AMS projects(NXP/TI) not 100% Digital projects(like AMD/Intel). We want someone working on higher nodes like 140nm, 180nm, 190nm etc. Need to know Digital basics like DFF (D Flipflop) functionality. Need to have experience in Cadence tools. Should know DFT insertion and have full chip tape out experience. Need to be able to put a project plan till final tape out. RESPONSIBILITIES Collaborate with design teams to translate design requirements and constraints into a robust physical implementation. Execute all aspects of physical design, including floor planning, power planning, place and route, clock tree synthesis, and static timing analysis. Leverage expertise in industry-standard tools such as Cadence Genus, Innovus, Modus, Voltus, and Tempus. Enhance design quality and efficiency by developing and maintaining automation scripts and flows using Python. Work closely with layout designers to guarantee adherence to design rules and layout constraints. Participate in design reviews, providing constructive feedback to elevate the overall design quality. Stay at the forefront of industry trends and advancements in digital backend flows, IC layout, and physical design methodologies. ESSENTIAL REQUIREMENTS Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in digital backend design, with a strong understanding of physical design methodologies and flows. Proficiency in using industry-standard digital backend tools, for example Cadence Genus, Innovus, Modus, Voltus, and Tempus. Strong scripting skills in Python or similar languages for automating design tasks. Familiarity with IC layout principles, design rules, and layout constraints..

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