Job
Description
At Capgemini Engineering, as a part of the global team of engineers, scientists, and architects, you will have the opportunity to work on innovative projects that help the world's most innovative companies unleash their potential. Your role will involve working independently on block levels analog layout design, with a focus on critical analog layout design of various blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, and more. You will be expected to have good LVS/DRC debugging skills and experience with verifications for lower technology nodes like 14nm FinFet and below. Additionally, you should have a strong understanding of concepts like Matching, EM, ESD, Latch-Up, Shielding, Parasitic, and short channel effects. Familiarity with EDA tools like Cadence VLE/VXL, PVS, Assura, and Calibre DRC/LVS is essential. You should be able to comprehend the impact of layout on circuit parameters such as speed, capacitance, power, and area, while ensuring high-quality layouts within design constraints. Experience in multiple Tape out support will be advantageous. Your role will also require good people skills and critical thinking abilities to resolve technical issues professionally. Excellent communication skills are necessary for timely execution with high-quality layout design. Key Responsibilities: - Work independently on block levels analog layout design including Floorplan, Routing, and Verifications. - Design critical Analog Layouts of blocks like Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, etc. - Debug LVS/DRC issues and perform other verifications for lower technology nodes like 14nm FinFet and below. - Understand concepts like Matching, EM, ESD, Latch-Up, Shielding, Parasitic, and short channel effects. - Utilize EDA tools such as Cadence VLE/VXL, PVS, Assura, and Calibre DRC/LVS effectively. - Consider layout effects on circuit parameters like speed, capacitance, power, and area. - Implement high-quality layouts within design constraints. - Provide support for multiple Tape outs, if required. - Demonstrate good people skills and critical thinking abilities to resolve technical issues professionally. - Ensure timely execution with high-quality layout design. Qualifications Required: - Strong experience in Analog Layout design. - Familiarity with TSMC 7nm, 5nm, 10nm, 28nm, 45nm, 40nm processes. - Proficiency in EDA Tools such as Cadence Virtuoso L, XL for Layout Editor and DRC, LVS, Calibre for Physical verification. - Additional experience in IO layout will be a plus. Capgemini is a global business and technology transformation partner, with a diverse team of over 340,000 members in more than 50 countries. With a strong heritage of over 55 years, Capgemini is trusted by clients to leverage technology and address a wide range of business needs. The company delivers end-to-end services and solutions, with expertise in AI, cloud, data, and industry-specific knowledge. Capgemini reported global revenues of 22.5 billion in 2023. At Capgemini Engineering, as a part of the global team of engineers, scientists, and architects, you will have the opportunity to work on innovative projects that help the world's most innovative companies unleash their potential. Your role will involve working independently on block levels analog layout design, with a focus on critical analog layout design of various blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, and more. You will be expected to have good LVS/DRC debugging skills and experience with verifications for lower technology nodes like 14nm FinFet and below. Additionally, you should have a strong understanding of concepts like Matching, EM, ESD, Latch-Up, Shielding, Parasitic, and short channel effects. Familiarity with EDA tools like Cadence VLE/VXL, PVS, Assura, and Calibre DRC/LVS is essential. You should be able to comprehend the impact of layout on circuit parameters such as speed, capacitance, power, and area, while ensuring high-quality layouts within design constraints. Experience in multiple Tape out support will be advantageous. Your role will also require good people skills and critical thinking abilities to resolve technical issues professionally. Excellent communication skills are necessary for timely execution with high-quality layout design. Key Responsibilities: - Work independently on block levels analog layout design including Floorplan, Routing, and Verifications. - Design critical Analog Layouts of blocks like Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, etc. - Debug LVS/DRC issues and perform other verifications for lower technology nodes like 14nm FinFet and b
