6 Zero Delay Jobs

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world's most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same. Job Description Your Role As a SoC GLS Verification Engineer , you will play a key role in verifying complex SoC designs through Gate-Level Simulation (GLS). You will work closely with design an...

Expert in implementing Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. In your new role you will: Responsible for SoC DFT Architecture definition/implementation/verification/silicon debug of SoC/Full Chip. Need to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. Responsible for ATPG, DRC analysis, Test coverage debug, Memory BIST implementation and verification. Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck-at/TDF/Bridging/Cell-aware/iddq fault models. Good debug skills in ZERO delay and SDF based scan/MBIST/JT...

Job Title: VLSI Verification Engineer Experience: 1 to 3 years Location: Hyderabad Job Description: We are seeking a highly motivated VLSI Verification Engineer with hands-on experience in circuit simulation, gate-level verification, and schematic analysis . The candidate will work on SPICE-based simulations, GLS with SDF back annotation, and transistor-level debugging to ensure design quality and sign-off readiness. Key Responsibilities: Develop, understand, and analyze block-level & memory schematics. Perform SPICE simulations (DC, transient) and correlate with gate-level models. Conduct gate-level simulations with SDF back annotation. Debug annotation issues, timing violations, and GLS fa...

Key Responsibilities: Perform gate-level simulations (GLS) for ASIC/SOC designs post-synthesis and post-layout. Validate timing, power-up behavior, clock gating, and low-power modes (with UPF/CPF ). Develop and execute GLS test plans including functional, scan, and ATPG pattern verification. Work closely with RTL design, DFT, STA, and backend teams for issue resolution. Debug timing-related issues in post-layout netlist simulations . Ensure zero-delay and SDF-annotated simulation coverage. Requirements: Strong experience in GLS verification at the netlist level with SDF annotation. Solid understanding of timing closure , STA concepts, and simulation tools. Proficient in SystemVerilog , scrip...

You have a total experience of 5 to 7 years with a minimum of 3+ years of SOC GLS experience. You have hands-on experience in GLS including Zero Delay, SDF, and PAGLS. Your strong debugging skills enable you to fix issues efficiently. In addition, you possess knowledge in SV/UVM and test bench flow. Your familiarity with EDA tools like Synopsys Verdi and Cadence NC Sim is commendable. It is expected that you have a good understanding of SOC Architecture. **Key Responsibilities:** - Hands-on experience in GLS including Zero Delay, SDF, and PAGLS - Excellent debugging skills and issue resolution - Knowledge in SV/UVM and test bench flow - Experience with EDA tools such as Synopsys Verdi and Ca...

Job Description Total experience (5 -7 years) with SOC GLS experience of minimum 3+ years Hands on experience in GLS (Zero Delay, SDF, PAGLS) Excellent debugging skills and fixing issues Knowledge in SV/UVM and test bench flow Good experience in EDA tools such as Synopsys Verdi, Cadence NC Sim. Understanding of SOC Architecture Education Qualification: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field.