28 Xilinx Vivado Jobs - Page 2

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology. InnoPhase Inc., DBA GreenWave Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best developing and implementing highly innovative SOC cellular radio integrated circuit products. Key Responsibilities: Individual contributor to develop Embedded Linux-based SW solutions for O-RAN Cellular base station radios. Assist with the definition, development & verification of FW/SW products. Establish unit level design, implementation & test strategies. Support integration & test and debug software for timely closure Work with the Applications team and customers to provide the necessary support. Job Requirements: 10+ years relevant work experience required. BE/B.Tech, M.Tech EC/CS required. Strong coding skills in C, C++, and/or Python. Experience with Embedded Linux Kernel, Driver & Application development. Cellular RAN development experience. Experience building and integrating SW for a multi-vendor environment e.g., some internal custom SW + Xilinx IP + 3rd-party / open-source SW. Experience with ARM or similar embedded SoC development environment. Excellent debugging skills. Comfortable with configuration management, version control & modern software development flow (e.g., Agile). Good communication, documentation & presentation skills. Prior experience with FPGA and/or Network Processor software development. Team player with a strong sense of urgency to meet product schedules. Be able to work productively and independently. Desirable Skills: Familiarity with ORAN M/C/S/U plane. Familiarity with netconf2, netopeer2 client/server, yang, SysRepo, SyncE, PTP, eCPRI, CPRI. Experience with development for PetaLinux (Xilinx-based Linux SW package) including development workflow incorporating Xilinx Vivado & Xilinx SDK. Experience with Xilinx Zynq platform, Vivado Tools (10G Ethernet IP). Understanding of FPGA HDL (VHDL, Verilog, System Verilog) and/or FPGA PL/RTL. Experienced in RTOS principles and concepts & hands-on experience in any RTOS. Prior System on a Chip (SoC) product development experience. Good understanding of cellular wireless protocols (MAC/PHY). Experience using command-line Git, GitLab & Jira tools. Benefits: Competitive salary and stock options. Learning and development opportunities. Employer-paid health Insurance. Earned, Casual, Sick & parental leaves.

Job Responsibilities : You will develop RTL code to implement FPGA-based digital designs , working from specification stage through to system integration. Projects will range from Mid to multi-million gates. Most projects include designing logic for latest generation of high speed serial protocols like PCIe gen5, Gen6, USB 3.2 Ethernet 10G/25G/100G, digital signal processing and control logic (bus interfaces and state machines) Understand the customer requirements and product definition Define architecture and detailed design spec based on requirements and various trade-offs Micro-architecture and coding of assigned module in VHDL/Verilog Write test bench for verifying design for complete scenario coverage Implementation of the design for porting on FPGA after required optimization based on available resources and timing closure requirement FPGA debugging and HW/SW integration Requirements: 6+ years of experience, including successful completion of FPGA based projects Coding experience in VHDL and/or Verilog is must Experience targeting Xilinx and/or Altera FPGAs required Familiarity with tools like Modelsim, Questasim, Xilinx Vivado, Planahead, Altera Quartus etc. is required Familiarity with debugging tools like Chipscope, Signal Tap, Logic analyzer, Scope, FPGA editor Implementation of designs with multiple clock domains is required Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed Experience in RTL implementation of DSP algorithms will be appreciated Experience in development of PCIe, USB, Ethernet transceivers, DDRx, ADC, DAC, AMBA-AXI, SRAM, USB, UART, I2C, SPI will be appreciated

Job Responsibilities : You will develop RTL code to implement FPGA-based digital designs , working from specification stage through to system integration. Projects will range from Mid to multi-million gates. Most projects include designing logic for latest generation of high speed serial protocols like PCIe gen5, Gen6, USB 3.2 Ethernet 10G/25G/100G, digital signal processing and control logic (bus interfaces and state machines) Understand the customer requirements and product definition Define architecture and detailed design spec based on requirements and various trade-offs Micro-architecture and coding of assigned module in VHDL/Verilog Write test bench for verifying design for complete scenario coverage Implementation of the design for porting on FPGA after required optimization based on available resources and timing closure requirement FPGA debugging and HW/SW integration Requirements: 6+ years of experience, including successful completion of FPGA based projects Coding experience in VHDL and/or Verilog is must Experience targeting Xilinx and/or Altera FPGAs required Familiarity with tools like Modelsim, Questasim, Xilinx Vivado, Planahead, Altera Quartus etc. is required Familiarity with debugging tools like Chipscope, Signal Tap, Logic analyzer, Scope, FPGA editor Implementation of designs with multiple clock domains is required Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed Experience in RTL implementation of DSP algorithms will be appreciated Experience in development of PCIe, USB, Ethernet transceivers, DDRx, ADC, DAC, AMBA-AXI, SRAM, USB, UART, I2C, SPI will be appreciated