104 Xilinx Jobs - Page 4

Job Summary: Drives the design chain value proposition by generating the greatest number of design wins in technologies and registrations for customers engaged in product design resulting in growing business. Interface with the engineering departments of customers and suppliers. Performs a variety of product, technical and engineering functions including but not limited to: pre/post sales support, research, design and development. Principal Responsibilities: Proactively develops and implements the technical sales account penetration strategy in each market presenting new products and technologies to current and potential customers; develop knowledge to uncover, understand, compare, and contrast the solutions (pre-component selection). Provide valuable participation in supplier/customer design review. Good understanding of customer needs relative to product(s), technology, direction, competition, design process and design cycle. Identify and develop relationships with all key technical decision makers and influencers in each account. Discover design requirements from the system level down to each individual element collaborating with the design, production and/or engineering departments to develop/execute technical strategies that help solve customer design challenges. Market supported lines to sales team by driving adoption of advocated solutions, with supplier partners, that meet customer needs and lead to increased design activity, design wins and sales growth. Proactively provides general application and product level sales training, proactively align with sales team in securing business. Communicate account calls with suppliers, account managers and/or inside sales. Identifies and tracks largest design opportunities from concept to production, utilizing all supplier resources to assure greatest potential for success. Creates presentations and other sales tools to enhance technical value and become a "trusted advisor" to both internal and external customers. Manages the product from beginning to end which involves communication and in-depth consultation with customers, sales and vendors. Research major industry players to be able to communicate to internal and external customers industry trends and directions. A thorough understanding of product lifecycles and the ability to design a full solution based on the customers expectation of product performance, lifecycles and total costs. Attend internal and external technical training to complete and maintain certification as necessary. Other duties as assigned. Job Level Specifications: Deep understanding of business, financials, products/services, the market or the needs/challenges of assigned accounts. Requires depth and/or breadth of sales expertise within a specialized product, service or account type. Requires a deep understanding of the full range of offerings that the organization and its competitors sell and that assigned customers buy. Recognized as a technical expert (by colleagues and customers) in one or several product/service areas. Complexity is extremely high (territory/account, products/services, sales or account management process); serves as team lead. Plans own territory or account approach and has input into colleagues' approaches; manages own and often others' resources. Leads others to solve complex problems; uses sophisticated analytical thought to exercise judgement and identify innovative sales solutions. Leads sales teams on negotiations to identify, pursue or manage accounts/ opportunities with extremely large size/strategic importance/risk of loss. Develops colleagues' understanding; acts as a role model for colleagues with less experience. Has extremely high authority/opportunity to set and negotiate product/service terms. Plans own territory or account approach and has input into colleagues' approaches; manages own and often others' resources. Serves as consultant to management and/or internal/external spokesperson for the organization on major initiatives related to policies, plans and long-range objectives. Impacts the relationship the organization has with its leading clients Impacts the relationship the organization has with its leading clients. Leads sales that have a significant impact on the function/region/division. Actions may impact the organization and its reputation. Effects of erroneous decisions may be long-lasting, influence the future course of the organization and/or require the expenditure of extensive additional resources. Work Experience: Minimum experience required is typically 8+ years with bachelor's or equivalent. This is typically the most senior sales position in the company and is reserved for the most experienced sales professionals. Education and Certification(s): Bachelors degree or equivalent experience from which comparable knowledge and job skills can be obtained.

Skills required: Candidate should have 3-10yrs experience Good Knowledge of multimedia frameworks like v4l2 and DRM framework in Linux . Experience in Linux device drivers. Strong knowledge in C. Hands-on experience with Configuration Management tool like GIT, Perforce. Knowledge on GStreamer multimedia framework Have an interest to constantly learn and share new findings. A quality mindset, ability for strategic thinking and a drive to always improve. Self-motivated Nice To Have: GStreamer application development for creating multimedia pipelines Responsibilities: The engineer will be responsible for the Development, debugging, bug fixing and testing of our Xilinx embedded distribution with Yocto flows.

Exp: 3 to 15 YrsLocation: Hyderabad / Bangalore The core skill set expected from the team is : Exceptional Digital fundamentalsHands on experience in System Design with FPGA devices with relevant FPGA EDA toolsExperience in designing and implementing FPGA based solutions in Microchip or Xilinx or Altera FPGAsWrite high quality code in Verilog/System Verilog, VHDL and C code for embeddedprocessors. Maintain existing code.Developing testbenches using Verilog/System Verilog and verifying validation designs in simulation environment using BFM/VIPExperience in using Synthesis, Placement constraintsSTA constraint definition and Timing closure for high speed designsValidation of FPGA based implementation on HW boardExperience in writing embedded FW programs in C/C++Strong Lab debug experience and enthusiasm & patience to solve systems level hardware issues using Lab equipment, Embedded debuggers and RTL debuggersBe conversant with on-chip debug toolsExperienced with scripting tcl/perlExposure to Version management systems, GitHub, SVNExcellent verbal and written communication skills in EnglishStrong technical background in silicon validation, failure analysis and debugUnderstand hardware architectures, use models and system level design implementations required to utilize the silicon feature s.

SOURCERIGHT TECHNOLOGIES (INDIA) PRIVATE LIMITED is looking for FPGA RTL Design Engineer to join our dynamic team and embark on a rewarding career journey. Research and draft blueprints, engineering plans, and graphics. Develop test prototypes. Identify solutions to improve production efficiency. Use design software to develop models and drawings of new products. Maintain existing engineering records and designs. Assess all engineering prototypes to determine issues or risks. Estimate cost limits and budgets for new designs. Supervise the manufacturing process of all designs. Coordinate with other engineers, management, and the creative department.

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology. InnoPhase Inc., DBA GreenWave™ Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products. Key Responsibilities: Individual contributor to develop Embedded Linux-based SW solutions for O-RAN Cellular base station radios. Design, develop, and optimize embedded Linux software for O-RAN-based cellular base station radios. Implement software solutions to interface with radio hardware, processing layers, and wireless protocols. Develop software for hardware abstraction layers, device drivers, and radio processing functionalities in the O-RAN stack (CUSM). Optimize embedded software for low-latency, real-time performance, and high throughput, ensuring the software meets strict timing and reliability requirements, focusing on memory management, CPU utilization, and power efficiency. Collaborate with hardware engineers, systems architects, and other software teams to ensure seamless integration of hardware and software for O-RAN base station radios. Develop and implement control, monitoring, and resource management systems that interact with the radio hardware ensuring compatibility and interoperability with other O-RAN-compliant elements. Assist with the definition, development & verification of FW/SW products. Establish unit level design, implementation & test strategies. Support integration & test and debug software for timely closure. Work with the Applications team and customers to provide the necessary support. Job Requirements: 15+ years relevant work experience required. BE/B.Tech, M.Tech – EC/CS required. Strong coding skills in C++ as mandatory, and/or Python Expertise in ORAN stack and M/C/S/U plane. Experience with Embedded Linux Kernel, Driver & Application development. Cellular RAN development experience. Experience building and integrating SW for a multi-vendor environment e.g., some internal custom SW + Xilinx IP + 3rd-party / open-source SW. Experience with ARM or similar embedded SoC development environment. Excellent debugging skills. Comfortable with configuration management, version control & modern software development flow (e.g., Agile). Good communication, documentation & presentation skills. Prior experience with FPGA and/or Network Processor software development. Team player with a strong sense of urgency to meet product schedules. Be able to work productively and independently. Desirable Skills: Familiarity with ORAN M/C/S/U plane. Familiarity with netconf2, netopeer2 client/server, yang, SysRepo, SyncE, PTP(IEEE1588), eCPRI, CPRI. Experience with development for PetaLinux (Xilinx-based Linux SW package) including development workflow incorporating Xilinx Vivado & Xilinx SDK. Experience with Xilinx Zynq platform. Experienced in RTOS principles and concepts & hands-on experience in any RTOS. Prior System on a Chip (SoC) product development experience. Good understanding of cellular wireless protocols (MAC/PHY). Experience using command-line Git, GitLab & Jira tools. Benefits: Competitive salary and stock options. Learning and development opportunities. Employer-paid health Insurance. Earned, Casual, Sick & parental leaves.

Roles and Responsibilities Good communication and analytical problem solving capability. Should be having hing level understanding for Design, develop and test various types of antennas for various applications. Conduct research and evaluate the performance of novel antenna design CST/ HFSS/ MATLAB software skills are preferred Develop and maintain technical documentation, including test plans and reports Should have knowledge related to fabrication and testing of the designed antenna. Good communication and analytical problem solving capability. Hands-on experience on FPGA / RTL Design involving verilog HDL,Cadence, Vivado ISE/Xilinx ISE, Modelsim and Synopsys will be an added advantage. Desired Candidate Profile B.E. or B.Tech with minimum one year of work experience. M.E. or M.Tech fresher. Perks and Benefits Salary, monthly grocery and medical insurance.

We are looking for an experienced Engineer with extensive experience with FPGA and emulation tasks of SoC preferably for Power related applications that has a thorough understanding of Xilinx Architecture and Timing closure strategies with the Verilog RTL coding skills and debug capabilities Exp-7

We are looking for an experienced Engineer with extensive experience with FPGA and emulation tasks of SoC preferably for Power related applications that has a thorough understanding of Xilinx Architecture and Timing closure strategies with the Verilog RTL coding skills and debug capabilities Exp-7

Proficient in RTL design using Verilog/SystemVerilog or VHDL In-depth knowledge of FPGA architecture and development flows (synthesis, P&R, timing analysis) Familiarity with high-speed interfaces and protocols like PCIe, Ethernet, DDR, AXI, AHB, SPI Required Candidate profile Experience with debugging tools like ChipScope, SignalTap, Logic Analyzer Proficiency in scripting languages like Python, Tcl, or Perl for automation of FPGA workflows

About The Role Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms. Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques. Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques. Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies. Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: 5+ years of experience in the verification of IPs Hands on experience in applying formal property verification for Ips signoff at least for 3 years Hands on experience in resolving convergence issues using FV on multiplies Managing and Guiding juniors in their verification task, Stakeholder management. Preferred Qualifications: Expertise in FV verification planning and strategies Good understanding of FV tools and capabilities Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Greetings From Dexcel Designs! We are inviting applications for FPGA Design and Verification Engineer Job Overview: We are seeking FPGA Design and Verification Engineers with 3-6 years of experience in RTL design, FPGA verification, and high-speed interface development . This role involves designing, implementing, and validating FPGA-based systems while working closely with cross-functional teams in hardware and embedded software development. Key Responsibilities: Develop and implement RTL designs for FPGA-based systems. Perform functional verification and validation of FPGA designs. Work on timing analysis, synthesis, and debugging of FPGA architectures. Collaborate with hardware, embedded software, and system architects to ensure seamless integration. Debug FPGA designs using industry-standard tools and methodologies . Technical Skills Required: Strong understanding of RTL design (Verilog/VHDL) and FPGA implementation. Experience with FPGA tools such as Vivado, Quartus, Synplify, ModelSim, and QuestaSim . Hands-on experience with at least one of the following high-speed interfaces : PCIe, SATA, USB, DisplayPort, JESD204B, SRIO MII/RMII/GMII/RGMII/SGMII/XAUI/RXAUI DDR/LPDDR/DDR2/DDR3, QDR memories Knowledge of FPGA debugging techniques, timing closure, and constraint handling . Preferred Skills: Experience in FPGA-based hardware design and testing . Exposure to SoC architectures and system-level integration . GFPGA Design and Verification Engineer ) and power integrity (PI) analysis .G

Must have exp in FPGA, VHDL, Embedded C.

Key Responsibilities: 1. Port ASIC designs to Xilinx FPGA platforms while ensuring performance and area efficiency. 2. Develop and optimize RTL (Verilog/VHDL) to meet FPGA design constraints. 3. Perform timing closure, static timing analysis (STA), and floorplanning. 4. Utilize Xilinx FPGA tool flow (Vivado) for synthesis, implementation, and bitstream generation. 5. Debug and validate FPGA implementations using simulation, hardware testing, and debugging tools (Chipscope, SignalTap, etc.). 6. Optimize FPGA performance through placement, routing, and power optimizations. 7. Collaborate with ASIC and system engineers to ensure seamless integration. 8. Good to have experience with Synplify for synthesis. 9. Experience with scripting languages (Tcl, Python, Perl) for automation is a plus.

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology. InnoPhase Inc., DBA GreenWave™ Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products. Key Responsibilities: Individual contributor to develop Embedded Linux-based SW solutions for O-RAN Cellular base station radios. Design and implement Front Haul Gateway on FPGA and Network Processor-based SoCs. Assist with the definition, development & verification of FW/SW products. Establish unit level design, implementation & test strategies. Support integration & test and debug software for timely closure Work with the Applications team and customers to provide the necessary support. Job Requirements: 5+ years relevant work experience required. BE/B.Tech, M.Tech – EC/CS required. Strong coding skills in C, C++, and/or Python. Experience with Embedded Linux Kernel, Driver & Application development. Cellular RAN development experience. Experience building and integrating SW for a multi-vendor environment e.g., some internal custom SW + Xilinx IP + 3rd-party / open-source SW. Experience with ARM or similar embedded SoC development environment. Excellent debugging skills. Comfortable with configuration management, version control & modern software development flow (e.g., Agile). Good communication, documentation & presentation skills. Prior experience with FPGA and/or Network Processor software development. Team player with a strong sense of urgency to meet product schedules. Be able to work productively and independently. Desirable Skills: Familiarity with ORAN M/C/S/U plane. Familiarity with netconf2, netopeer2 client/server, yang, SysRepo, SyncE, PTP, eCPRI, CPRI. Experience with development for PetaLinux (Xilinx-based Linux SW package) including development workflow incorporating Xilinx Vivado & Xilinx SDK. Experience with Xilinx Zynq platform, Vivado Tools (10G Ethernet IP). Understanding of FPGA HDL (VHDL, Verilog, System Verilog) and/or FPGA PL/RTL. Experienced in RTOS principles and concepts & hands-on experience in any RTOS. Prior System on a Chip (SoC) product development experience. Good understanding of cellular wireless protocols (MAC/PHY). Experience using command-line Git, GitLab & Jira tools. Benefits: Competitive salary and stock options. Learning and development opportunities. Employer-paid health Insurance. Earned, Casual, Sick & parental leaves.

As an FPGA & Board Design Engineer, you must develop new hardware designs, including system design, CPLD/ FPGA or processor design, and board-level analog/ digital circuit design for embedded systems/ boards. You have to develop detailed specifications based on requirements and implement Hardware designs in accordance with those defined requirements and/or specifications. Your duties include Schematic design generation and entry, netlist generation, and close interaction with the CAD team for layout review and feedback. Perform simulation activities including timing analysis, behavioural, and functional simulations. Develop test benches and other test tools as needed to complete the verification of FPGA designs. Carry out proto H/W bring-up with support from firmware engineers. REQUIREMENTS B.Tech. or M.Tech. EE with 2+ years of FPGA experience including implementation, synthesis, and timing closure. Proficiency in Verilog, VHDL and System Verilog. Proficiency in Synopsys Synplify, Xilinx Vivado, ISE Hands-on with FPGA debug methodologies, such as ChipScope. Proficient in Schematic capture tools like Orcad/Altium Hands-on experience with lab debug equipment such as oscilloscopes and logic analyzers. Strong scripting skills in Perl/Python. Experience in test bench design and implementation Knowledge of high-speed interfaces including PCIe, Ethernet, and DDR3/4. Knowledge of low-speed interfaces including SPI, IIC, and UART. Knowledge and experience designing with Altera and Xilinx FPGAs. Detail-oriented individual with good interpersonal skills and excellent written and verbal communications skills.

Skills required: 1. Should have worked on USRP N310/X310 (N3xx/X3x0) 2. In-depth Knowledge of FPGA Architecture 3. Able to write own RTL custom HDL or drops in IP a) VHDL, Verilog, System,Verilog, Vivado HLS b) Xilinx IP, Vivado Block Diagram 4. Should have developed RFNoC Block 5. Have working knowledge of USRP Hardware Driver (UHD) 6. Able to write custom FPGA logic in RFNoC Blocks 7. Able to use library of existing RFNoC Blocks a) FFT, FIR, Signal Generator, Fosphor 8. Have understanding of GNU Radio interface to RFNoC Block 9. FPGA debugging and HW/SW integration 10. Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed 11. In-depth knowledge of XILINX ZYNQ 71xx/pl-kINTEX-7 based RFNoC architecture is must. 12.Understand Customer requirements, define architecture and detailed design 13. Good Customer Communication Skills 14. Working knowledge of Agile.

Digantara is a leading Space Surveillance and Intelligence company focused on ensuring orbital safety and sustainability. With expertise in space-based detection, tracking, identification, and monitoring, Digantara provides comprehensive domain awareness across regimes, allowing end users to have actionable intelligence on a single platform. At the core of its infrastructure lies a sophisticated integration of hardware and software capabilities aligned with the key principles of situational awareness: perception (data collection) , comprehension (data processing) , and prediction (analytics) . This holistic approach empowers Digantara to monitor all Resident Space Objects (RSOs) in orbit, fostering comprehensive domain awareness. Digantara seeks an FPGA design Engineer to design and develop RTL modules for satellite payload electronics. The engineer will implement image processing algorithms and suitable data, control interfaces between the payload the satellite bus. Why Us Competitive incentives, galvanizing workspace, blazing team, frequent outings pretty much everything you have heard about a startup + you get to work on space technology. Hustle in a well-funded startup allowing you to take charge of your responsibilities and create your moonshot. Ideal Candidate: Someone with expertise in FPGA design for the satellite payload electronics/ground-based imaging systems. Responsibilities: Design and develop high-performance RTL modules for the FPGA-based payload electronics, to accomplish on-board image capture and processing. Develop high quality RTL and efficient custom IP blocks in VHDL/Verilog for AMD-Xilinx/Microchip FPGA target devices. Implement high-speed interfaces with a processor such as SerDes, Gigabit ethernet, PCIe, and AXI-4/AXI-4 Lite interface. Carry out Synthesis, Place and Route, static timing analysis (STA) and close the timing requirements of the FPGA design. Collaborate with hardware, embedded software, and image processing engineers to generate RTL design requirements, architecture, and test plans. Document the FPGA design, verification and validation, board level test results throughout the development lifecycle. Required Qualifications B.Tech/B.E in Electronics Engineering or M.Tech/M.E or PhD in Microelectronics/Embedded systems/VLSI. 4 to 6 years of demonstrated experience in RTL design and development for FPGA based digital systems. Strong proficiency in VHDL/Verilog based digital logic implementation with expertise in FPGA design flow using Vivado/Libero EDA tools. Deep understanding of FPGA architecture, Synthesis and Static Timing Analysis, Clock domain crossing techniques, and timing closure. Strong expertise in troubleshooting logical and timing observations during the development lifecycle. Proficiency in working with FPGA/SoC development kits and electronic test equipment. Preferred Skills Familiarity with digital image processing and image compression implementation on FPGA. Experience in developing reliable and robust FPGA designs for satellite payloads is a significant plus. Experience with Questasim or similar tools for functional verification and code coverage analysis. Knowledge of Embedded software development in C/C++ and algorithm implementation in MATLAB/Python. Knowledge of the latest advancements in FPGA based payload electronics development. Familiarity with the standards for satellite hardware development is an advantage. General Requirements Ability to work in a mission-focused, operational environment. Ability to think critically and make independent decisions. Interpersonal skills to enable working in a diverse and dynamic team. Maintain a regular and predictable work schedule. Writing and delivering technical documents and briefings. Verbal and written communications skills as well as organizational skills. Travel occasionally as necessary. Job Location: Hebbal, Bengaluru. Work Type: WFO with alternate Saturdays.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Additional About The Role : Minimum Qualifications Bachelor's degree in Science, Engineering or closely related field Experience with digital design and RTL development, Experience with front end EDA tools such as Synopsys Next Generation tools, Conformal LEC, Synopsys Formality and Synopsys PrimeTime Preferred Qualifications Knowledge and experience of graphics design and development Proficient in Perl, TCL and shell scripting Excellent interpersonal and team skills yet able to work independently and able to problem solve complex, unique and detailed issues Be Familiar with The latest EDA tools for synthesis, formal verification, timing analysis and physical design

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a "CPU Core Validation Engineer" you would be part of CPU Validation team in CPU org working on validation of CPU core pipeline arch and micro arch features. Roles and Responsibilities: Develop detailed test plan considering the IP arch and uarch features. Work with CPU design and verification teams to develop CPU bring up and functional validation test plans for the IP owned. Develop validation methodology and test contents to exercise on emulators during pre-Si phase and on Silicon. Work with SOC bring up teams, software teams to plan CPU core features bringup and end to end validation. Triage and debug failures on Silicon. Develop test contents and testing strategies to assist validation of CPU on silicon. Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs. Work with design team to suggest, architect new debug features to improve future CPU bringup"™s. Minimum Requirements: BA/BS degree in CS/EE with 5+ years"™ experience. 5+ Experience in Silicon Validation and bring up. Implementation of assembly, C/C++ language embedded firmware Experience with software tool chain including assemblers, C compilers, Makefiles, and source code control tools. Preferred Requirements: Good understanding of micro-processor architecture, in domains such as:Cache Coherence, Memory ordering and Consistency, Prefetching, Branch Prediction, Renaming, Speculative execution, and Address Translation/Memory Management. Knowledge of Random Instruction Sequencing (RIS) and testing a given design, at the Block/Unit-level and Subsystem/Chip-level for proving correctness. Experience in writing Test plans and Assembly code. Ability to develop and work independently on a block/unit of the design Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Position Overview This role focuses on developing and verifying Verilog RTL for protocol conversionspecifically converting from common protocols like AHB/AXI/APB to a proprietary protocol (UPI). It also includes FPGA mapping, synthesis, timing analysis, place and route, and overall system-level validation using Xilinx FPGA platforms. Responsibilities Verilog RTL Development & Verification: Develop RTL for protocol conversion (AHB/AXI/APB to UPI). Design and verify both serial and parallel interfaces to meet company specifications. FPGA Mapping & Validation: Perform synthesis, mapping, timing analysis, and place & route (PnR) on Xilinx series 4 or 5 FPGAs. Generate and program the FPGA bitstream. System-Level Verification: Run system-level tests to validate FPGA transactions and address any functional, timing, or related issues. Additional (Plus): Utilize knowledge of Quad SPI Flash memory protocols and programming as needed. Requirements At least 5 plus years of experience. Solid experience in Verilog RTL design and verification. Proven skills in FPGA mapping and validation using Xilinx FPGAs. Familiarity with protocol conversion techniques and interface design. Understanding of memory protocols (e.g., Quad SPI Flash) is an advantage. Location preferably in Phoenix area or Silicon Valley or India – Ahmedabad/Bangalore/Pune or Europe

Job Description: Understand customers requirements /specifications /tender enquiry. Define DSP, System and Board architecture. Project ownership from concept to delivery. This includes identifying risks, dependencies, creating mitigation plan, tracking project schedule, discussions with customers, design reviews. Partition the algorithms for implementing in FPGA and/or in SW. Identify the building blocks & Signal Processing functions. Provide estimates on FPGA resources, computation bandwidth, and memory bandwidth. Create module level details from architecture, coding, simulation and perform peer reviews. Apply the methodologies for design, verification or validation. Define, create and maintain all project related documentation, especially design documents with detailed analysis reports. Provide support to customer during integration phases at test sites and support to production teams. Defining the architecture of RTL functions HDL Coding Simulation and Implementation Testing on board and debugging Professional Skills: VHDL Knowledge Xilinx tools for synthesis and implementation Thorough understanding of Xilinx FPGAs Functional Simulation Hardware Design : Logic Design & Debugging expertise FPGA Design : VHDL/Verilog RTL Coding, System C/ System Verilog FPGA Synthesis & PAR Tools Implementing DSP algorithms in FPGA environment for Radar and Electronic Warfare systems. Modeling the algorithms in Octave/MATLAB, generating test vectors, visualizing data. Working knowledge on interfacing with ADCs and DACs and interpreting their performance. Fluency, good communication & presentation skills. Configuration/Version control tools like SVN

Role & responsibilities As an FPGA Engineer, you will be responsible for task such as digital signal processing, debugging, RTL design, and electrical engineering Preferred candidate profile Perks and benefits

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology. InnoPhase Inc., DBA GreenWave Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best developing and implementing highly innovative SOC cellular radio integrated circuit products. Key Responsibilities: Individual contributor to develop Embedded Linux-based SW solutions for O-RAN Cellular base station radios. Assist with the definition, development & verification of FW/SW products. Establish unit level design, implementation & test strategies. Support integration & test and debug software for timely closure Work with the Applications team and customers to provide the necessary support. Job Requirements: 10+ years relevant work experience required. BE/B.Tech, M.Tech EC/CS required. Strong coding skills in C, C++, and/or Python. Experience with Embedded Linux Kernel, Driver & Application development. Cellular RAN development experience. Experience building and integrating SW for a multi-vendor environment e.g., some internal custom SW + Xilinx IP + 3rd-party / open-source SW. Experience with ARM or similar embedded SoC development environment. Excellent debugging skills. Comfortable with configuration management, version control & modern software development flow (e.g., Agile). Good communication, documentation & presentation skills. Prior experience with FPGA and/or Network Processor software development. Team player with a strong sense of urgency to meet product schedules. Be able to work productively and independently. Desirable Skills: Familiarity with ORAN M/C/S/U plane. Familiarity with netconf2, netopeer2 client/server, yang, SysRepo, SyncE, PTP(IEEE1588), eCPRI, CPRI. Experience with development for PetaLinux (Xilinx-based Linux SW package) including development workflow incorporating Xilinx Vivado & Xilinx SDK. Experience with Xilinx Zynq platform. Experienced in RTOS principles and concepts & hands-on experience in any RTOS. Prior System on a Chip (SoC) product development experience. Good understanding of cellular wireless protocols (MAC/PHY). Experience using command-line Git, GitLab & Jira tools. Benefits: Competitive salary and stock options. Learning and development opportunities. Employer-paid health Insurance. Earned, Casual, Sick & parental leaves.

Develops RTL Designs within environments that have constrained timing and memory resources, designs and implements reusable code, performs design and code reviews, as well as tests and validates product implementations. Understanding of high-level software requirements and low-level software requirements. Capable of developing software verification test cases and test procedures. Analyse and enhance the efficiency, stability, and scalability of system resources. Good understanding of the embedded systems serial protocols (UART/ USB/SPI/i2C/ CAN Integrate and validate new product designs. Support software QA and optimize I/O performance. Provide post-production support. Interface with hardware design and development. Improve system efficiency and stability after development. Collaborate with customers to create systems based on their needs Requirements and skills: Bachelors degree in Electrical/Electronics/ Computer Engineering, Computer Science or a related field. Hands on Exp in RTL design in Verilog, VHDL, ASIC/FPGA experience If ASIC experience, then Lint/CDC tool experience If FPGA experience, then Xilinx or Altera/Intel , Microsemi FPGA parts and tools RTL debug experience Knowledge of at least one industry standard protocols like I2C/SPI/UART, PCIe, MIPI, AXI, Ethernet Adequate knowledge of reading schematics and data sheets for components. Strong interpersonal and writing skills. Ability to work as part of a team and as an individual. Exceptional analytical and problem-solving skills. Self-motivated and passionate about work and embedded systems.

Responsibilities The engineer will be responsible for the Development, debugging, bug fixing and testing of our Xilinx embedded distribution with Yocto flows. Skills Must have Candidate should have 3-10yrs experience Good Knowledge of multimedia frameworks like v4l2 and DRM framework in Linux . Experience in Linux device drivers. Strong knowledge in C. Hands-on experience with Configuration Management tool like GIT, Perforce. Knowledge on GStreamer multimedia framework Have an interest to constantly learn and share new findings. A quality mindset, ability for strategic thinking and a drive to always improve. Self-motivated Nice to have GStreamer application development for creating multimedia pipelines Other Languages English: B2 Upper Intermediate Seniority Regular Refer a Friend Positive work environments and stellar reputations attract and retain top talent. Find out why Luxoft stands apart from the rest. Recommend a friend Related jobs View all vacancies Senior UEFI/BIOS Developer C Embedded India Bengaluru Regular C Embedded / C++ Software Engineer C Embedded Poland Remote Poland Regular C Embedded / C++ Software Engineer C Embedded Turkiye Remote Turkey Hyderabad, IN, India Req. VR-112288 C Embedded Automotive Industry 03/03/2025 Req. VR-112288 Apply for Multimedia Engineer in Hyderabad, IN *