6.0 - 9.0 years

0 Lacs

hyderabad, telangana, india

On-site

BE/B.Tech in ECE /M.Tech in VLSI with 6 to 9 years experience in Analog Mixed Signal Verification Very Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks Very Good experience in Analog Mixed Signal verification simulation tools Good experience in System Verilog, UVM methodologies Able to train the team members and guide them to the solutions for problems Good experience in creating the AMS Verification environment and able to create AMS Verification environment from scratch. Good experience in Gate level netlist simulation Experience in Python, Perl, Shell scripting is added advantage. Good communication and documentation skills

Posted 4 weeks ago

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AMS Verification Engineer Coventine Digital

5.0 - 10.0 years

6 - 15 Lacs

Pune, Bengaluru

Work from Office

Key Responsibilities: Develop AMS verification environments from the ground up using SystemVerilog/UVM Own and execute test planning, AMS setup, and mixed-signal simulation Work on SerDes verification involving high-speed protocols (PCIe, USB 3.0, MIPI, etc.) Model and verify analog/mixed-signal blocks using wreal , RNM , and Verilog-A Perform simulations using VCS Primesim AMS and Primesim XA tools Collaborate closely with analog, digital, and system teams for integrated AMS verification

Posted 3 months ago

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