ASIC/RTL Design Engineer(DDR)- Staff Qualcomm

2.0 - 7.0 years

0 Lacs

karnataka

On-site

Qualcomm India Private Limited is looking for an experienced ASIC Design Engineer to join their Engineering Group, Hardware Engineering division. As an ideal candidate, you should hold an MTech/BTech in EE/CS with a minimum of 7 years of experience in ASIC design. Your responsibilities will include micro-architecture development, RTL design, front-end flows, synthesis, DFT, FV, and STA. A good understanding of DDR families and generations, as well as protocols like AHB/AXI/ACE/CHI, will be advantageous. Experience with post-silicon bring-up and debug is a plus. You should be able to collaborate effectively with global teams and possess strong communication skills. Hands-on experience in Multi Clock designs, Asynchronous interface, and Low power SoC design is essential for this role. Your key responsibilities will involve micro-architecture & RTL development, validation for linting, clock-domain crossing, and DFT rules. You will work closely with the functional verification team on test-plan development and waveform debugs at various levels. Experience in constraint development, timing closure, UPF writing, power aware equivalence checks, and low power checks is required. Additionally, you will be supporting performance debugs and addressing performance bottlenecks, along with providing assistance in sub-system, SoC integration, and chip-level debug. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. Qualcomm expects all employees to adhere to applicable policies and procedures, including those related to the protection of confidential information. If you meet the following qualifications and have the required experience, we encourage you to apply for this exciting opportunity at Qualcomm India Private Limited.,

Posted 1 week ago

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