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4.0 - 9.0 years

15 - 30 Lacs

hyderabad, malaysia

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RTL Design Engineer 4+yrs experience Location: Hyderabad_onsite Malayasia Advanced RTL Design and DFT trainee, looking forward to build a career in the VLSI domain. To work with full determination and dedication, to achieve organization as well as personal goals. Skills : Verilog, Design for Testability (DFT), RTL Coding, STA, System Verilog, C, FPGA design Hands-on experience : Router 1x3 - Design using Verilog, RISCV32I Processor- RTL Design and DFT

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