Develops custom layout design of analog blocks, complex digital, mixed signal blocks, standard cell libraries, or memory compilers (e.g., bit cells, SRAMs, Register Files). Performs detailed physical array planning, area optimization, digital block synthesis, critical wire analysis, custom leaf, cell layout, and compiler assembly coding. Conducts complete layout verification including design rule compliance, SoC integration specs, electron migration, voltage drop (IR), selfheat, ESD, and other reliability checks. Uses custom autorouters and custom placers to efficiently construct layout. Provides feedback to circuit design engineers for new feature feasibility studies and implements circuit enhancement requests. Develops and drives new and innovative layout methods to improve productivity and quality. Troubleshoots a wide variety of issues up to and including design and tool/flow/methodology issues used for layout design. Qualifications A BS/BE/BTech in Electronics Engineering with exposure to designing and optimizing VLSI layout at the cell and/or block level is required. Additional Desired Qualifications Good knowledge of VLSI process and device physics Exposure to physical verification tools, including DRC, LVS, ERC, density, and DFM checks. Unix and shell scripting exposure Knowledge of CAD layout tools eg Cadence Virtuoso Synopsys Custom Compiler any other industry-standard layout development tool Knowledge of scripting languages TCL, Perl, Skill, Python for design automation is a plus
