536 Vlsi Jobs - Page 18

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s microprocessor chip design team. As a member of DFT team, you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expertise in analysing and resolving DRCs/TSVs . Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues. Hands-on experience with Gate-Level DFT verification, both with and without timing annotations. Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery . Hands on experience on industry standard tools used for DFT features Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks. Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs. Excellent analytical and problem-solving skills, with a keen attention to detail. Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Preferred technical and professional experience Experience working with ATE engineers for silicon bring up, silicon debug and validation. Experience in processor flow and post silicon validation

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: Analog Circuit design.Experience3-5 Years.

Job Description Amrita Vishwa Vidyapeetham invites application for Assistant Professors/Associate Professors/Professors in the Department of Electronics and Communication Engineering at Amrita School of Engineering, Bengaluru Campus. Required Area VLSI (Analog and RF) Advanced Communication and Networks Signal and Image Processing Cloud Computing/IIoT Cyber Physical Systems Advanced Embedded Systems Responsibilities Conducting research in the field of specialization and related area as mentioned above. Teaching and mentoring students in undergraduate and graduate programs (including PhD) Collaborating with academia and industry within and outside country on research projects Publishing research findings in reputed conferences and journals Requirements Strong fundamentals in ECE and related area Demonstrated research experience in relevant areas Proven track record of taking initiatives and driving projects Good communication and interpersonal skills Ability to work effectively in a team and collaborate with colleagues

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Deliver No. Performance Parameter Measure 1. Verification Timeliness, Quality and coverage of verification, Compliance to UVM standards, Customer responsiveness 2. Project documentation and MIS 100% on time MIS & report generation Complete Project documentation (including scripts and test cases) 3. Team % trained on new skills, Team attrition %, Employee satisfaction score (ESAT) Mandatory Skills: Semiconductor Integration.

We are now looking for a Senior Power Verification Engineer. NVIDIA is seeking elite ASIC Verification Engineers to verify the design and implementation of low power features for the world s leading Smart-NICs and DPUs which help accelerate network performance while reducing the CPU overhead of Internet Protocol (IP) packet transport, freeing more processor cycles to run applications. These networking processors also embed innovative hardware engines that offload and accelerate security with in-line encryption/decryption. With unmatched RDMA over Converged Ethernet (RoCE) performance, NVIDIA Smart-NICs and DPUs deliver efficient, high-performance remote direct-memory access (RDMA) services to bandwidth- and latency-sensitive applications! The Networking Chip Design in India is a new team which is growing at a fast pace! What you ll be doing: Work on structural and functional verification of low power aspects of NVIDIA s family of smartNICs and DPUs. Come up with test plans and coverage plans of these features. Write test cases, test bench components like assertions and coverage points, and own verification convergence. Collaborate with system level and unit level teams to cover the features well from functional, electrical, performance, and noise aspects. Be responsible for debugging waves to analyse power consumed by unit IP s. Work with architects, designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks. Validate/Correlate the effectiveness of the low power features on silicon. What we need to see: BS/MS or equivalent experience with specialisation related to Low Power techniques and Verification. 5+ years of experience. Fundamental understanding of power basics including transistor-level leakage/dynamic characteristics of VLSI circuits. Knowledge of power intent formats - UPF/CPF. Experience in Static Power check - tools like VCLP/MVRC or similar. Hands-on knowledge in Power aware dynamic verification - NLP/MVSIM or similar tools. Experience in design and verification tools (VCS, XCelium or equivalent simulation tools, Verdi, Indago or other debug tools). Familiarity with low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS). Exposure to Cluster / Sub-system / Fullchip / SOClevel verification environments Ways to stand out from the crowd: Prior experience of SmartNICs (or DPU) and/or high-speed interconnects. Good software programming skills. Python/Perl/C++ preferred. Confident debugging and problem-solving skills. Good interpersonal skills and ability & desire to work as an excellent teammate. Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www. nvidiabenefits. com/ NVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

Notice Period : Immediate - 15 Days Key Responsibilities : - Software Development : Implement software solutions using Python programming language. - Test and Validation : Design and execute comprehensive test cases to ensure software quality. - Technical Documentation : Create clear and concise technical documentation. - Customer Support : Respond to customer inquiries and resolve issues in a timely manner. - Automation : Automate design steps within the VLSI CAD flow. - Agile Development : Work in Agile Scrum teams and follow Agile methodologies. - Collaboration : Collaborate with customers to align on project requirements and present project updates. - Quality Assurance : Adhere to coding standards and quality processes. Required Skills and Experience : - 5+ years of experience in software development. - Strong proficiency in Python programming language. - In-depth knowledge of object-oriented programming concepts. - Excellent understanding of Unix/Linux operating systems and shell scripting. - Experience with development tools like Git-BitBucket, JIRA, and Confluence. - Strong problem-solving and analytical skills. - Excellent communication and collaboration skills. Mandatory Skills : - Python Mandatory Expert 60m - Software Development Mandatory Expert 60m - Unix Mandatory Intermediate 48m - Cadence Optional Beginner 12m - Logical Physical Synthesis Optional Beginner 12m Highly Desired Skills : - Experience with CI/CD tools like Jenkins, GitLab, StockStorm, and Camunda. - Background in semiconductor, EDA, or tool development domains. - Experience working in Agile Scrum teams. - Understanding of VLSI CAD flows.

Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You'll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 10-15 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 9-12 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. You will be responsible for functional verification involving coherent and non-coherent IP designs. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol.

Managing a team of software engineers to develop and optimize test vectors for VLSI chip testing. Coordinating with multiple teams to ensure seamless integration and functionality of software solutions. Programming in C/C++ to develop high-quality software for detecting manufacturing defects in VLSI chips. Conducting rigorous testing to ensure the reliability and performance of software solutions. Learning from existing documentation and source code to integrate new ideas and improve algorithms. Engaging in continuous improvement of software quality and performance. The Impact You Will Have:Enhancing the reliability and performance of VLSI chips used in advanced technologies like AI and automated cars. Ensuring the highest quality of integrated circuits delivered to major design houses. Driving innovation in chip design and validation through optimized software solutions. Contributing to the success of Synopsys cutting-edge technology in the semiconductor industry. Improving the efficiency and effectiveness of software development processes. Fostering a collaborative and high-performing engineering team. What You will Need: Proficiency in programming, preferably in C/C++. Experience in managing and leading small teams of software engineers. Strong knowledge of data structures and algorithms. Good understanding of digital logic and VLSI concepts. In-depth understanding of timing analysis in VLSI.

The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success. Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests. You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Responsibilities & Skills: (Design Verification Engineer) The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL). Prior experience in simulation/emulation using these languages. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools. Experience in process automation with scripting. Experience with SystemVerilog, C++, UVM. Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog. Experience designing and implementing complex functional verification environments is required. Knowledge of protocols like PCIe, USB3/4, DP an added advantage. Qualifications Minimal qualification requires B. Tech or M. Tech/B.E./M.E. with 3-6 years of experience in relevant experience. Behavioral skills required. Must possess strong written, verbal and presentation skills. Ability to establish a close working relationship with both customer peers and management. Explore what s possible to get the job done, including creative use of unconventional solutions. Work effectively across functions and geographies. Push to raise the bar while always operating with integrity.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Product Validation Engineer Location: Bangalore Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary As PV engineer, this person will be responsible for product validation [quality engineering] owning validation from test plan creation, test automation to bug tracking, follow-up and closing summary. The ideal candidate is expected to have understanding of semiconductor verification flow. Job Responsibilities Focus on quality of physical validation tool Pegasus by analyzing on existing functionality/regressions for customer deliverables and report failures in bug tracking system. Maintain regression tests with regular test cycles and integrate customer test cases as part of regression suites. Working closely with PE and R&D to develop test plan of new features and methodology for testing coverage improvement. Experience and Technical Skills required 4+ to 7 years experience in developing and supporting physical verification activities. Have 3+ years of experience in VLSI back-end domain Be expert in layout and physical verification concepts (DRC/FILL/LVS/PERC) Have solid working experience with UNIX and skilled in shell/perl/tcl/python scripting language Good communication, strong solving skill and working as a team player Strong knowledge of Cadence Virtuoso is a big plus Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronics Behavioral skills required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We re doing work that matters. Help us solve what others can t. Role: Blockchain Quality Assurance Engineer Industry Type: IT Services & Consulting Department: Engineering - Software & QA Employment Type: Full Time, Permanent Role Category: Quality Assurance and Testing Education UG: B.Tech/B.E. in Production/Industrial PG: M.Tech in Electronics/Telecommunication Key Skills Unix VLSI Physical verification Test planning System design Perl product validation Test cases Automotive Python

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Product Validation Engineer Location: Bangalore Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary As PV engineer, this person will be responsible for product validation [quality engineering] owning validation from test plan creation, test automation to bug tracking, follow-up and closing summary. The ideal candidate is expected to have understanding of semiconductor verification flow. Job Responsibilities Focus on quality of physical validation tool Pegasus by analyzing on existing functionality/regressions for customer deliverables and report failures in bug tracking system. Maintain regression tests with regular test cycles and integrate customer test cases as part of regression suites. Working closely with PE and R&D to develop test plan of new features and methodology for testing coverage improvement. Experience and Technical Skills required 4+ to 7 years experience in developing and supporting physical verification activities. Have 3+ years of experience in VLSI back-end domain Be expert in layout and physical verification concepts (DRC/FILL/LVS/PERC) Have solid working experience with UNIX and skilled in shell/perl/tcl/python scripting language Good communication, strong solving skill and working as a team player Strong knowledge of Cadence Virtuoso is a big plus Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronics Behavioral skills required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We re doing work that matters. Help us solve what others can t. Role: Blockchain Quality Assurance Engineer Industry Type: IT Services & Consulting Department: Engineering - Software & QA Employment Type: Full Time, Permanent Role Category: Quality Assurance and Testing Education UG: B.Tech/B.E. in Production/Industrial PG: M.Tech in Electronics/Telecommunication Key Skills Unix VLSI Physical verification Test planning System design Perl product validation Test cases Automotive Python

Job Description Role: Senior Manager, IO Design Memory Technology Competencies: Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering (VLSI Design) Extensive Hands-on design experience in IO Design(LVCMOS, HVCMOS, DDR, LVDS) 15+ years of Experience on handling IO designs, projects working with BU, Stake holders NAND Flash Design knowledge is plus Expertise in ESD, Powerbus, Floor plan, Layout guidelines Expertise, knowledge of advanced DDR algorithms : Training modes and DFE/CTLE/Compensation Techniques, Clock skew techniques Management and Lead experience to handle Team of IO engineers Experience in working with cross geo, cross team functions and stake holder management Expertise with package/board/Power integrity /signal integrity constraints is a plus. Strong communication skills & circuit design knowledge is preferred. Tool knowledge: spice tools: finesim, hspice & other flows Good to have: Lead team of experienced IO Design Engineers Strategic development of next generation IO for scaling speed Build Best in Class IP Design Handling BU communication on all IO Roadmap, RMA, FA Drive E/E IO Design capability and execution till Silicon to Productization Qualifications B.TECH/M.TECH in Electrical / Electronics / VLSI / Microelectronics with 15+ years of experience

High speed VLSI/SBC/Analog/Digital/RF circuit design according to design rules. Design of product/card schematics. Preparation of related hardware design documents, document review. Leading or assisting through board bring up, helping resolve hardware issues. Review of PCB layout, BOM and other hardware documents. Engaging with in-house or third-party lab for product qualification as per teststandards. Required Skills: Knowledge of Orcad / Altium, Protel or other design tools. Well versed with EMC design techniques and signal integrity issues. Experience with hi-speed processor board/sbc design, aware of clock stability issues having worked with high speed RAM/Flash/PHY and other peripherals. Well versed with EMC design techniques and signal integrity issues. Min. 3 years hands-on in hardware development cycle, hardware debugging, natural ability to solve hardware problems. Experience in EMC testing, having successfully worked on product qualification for CE or IEC or MIL 461E test standards RequiredQualification and Experience: BE/B. Tech/M. Tech in Electronics / ETC / Instrumentation. Apply Now

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Deliver comprehensive training on VLSI Design and Verification, covering topics like Digital Design, Verilog/System Verilog, RTL Design, and UVM. Prepare, update, and structure course materials and assignments as per industry standards.

Semicon Technical Program Manager | Bangalore or Hyderabad | Experience: 7 to10 Years Are you a hands-on technical expert who thrives at the intersection of Digital Design and Program Leadership ? We're looking for a Semicon Technical Program Manager to drive end-to-end execution across high-impact SoC design programs. This is a billed, customer-facing role that goes beyond task trackingyoull own milestones, lead cross-functional sync-ups, and bring structure to complex digital engineering workflows. What You’ll Do: Drive technical coordination across RTL, DV, PD, and STA teams. Track and manage project milestones, deliverables , and dependencies. Lead technical meetings , ensuring alignment between engineering functions. Support internal leadership with timely status updates and reporting. Contribute to program governance , documentation, and issue resolution. What You’ll Need: 7–10 years of experience in Digital Design (preferably PD-focused). Solid understanding of RTL, DV , and Physical Design flows. Prior exposure to program or project management in a technical setting. Excellent communication and stakeholder management skills. Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com

Designation: Technical Support Engineer - VLSI Experience : 0-1 Years Education : B.tech/ BE- or M.Tech VLSI. ECE/ Diploma in Mechatronics/ECE Industry Type: Education / E-Learning / Semiconductor Category: Technical Job Description Responsible for development and support of Projects. Responsible for debugging the source codes in Verilog, SV, and UVM. Responsible for Monitoring the trainee's progress. Will be a point of contact for trainees to query on Technical concepts. Desired Candidate Profile Sound Knowledge on Verilog, SV, Digital ,UVM / Back-end design Good communication skill. Should be good in Digital Electronics. For more details, kindly contact 7406043555, fiza@maven-silicon.com

This position is with ASIC design physical implementation (PD) team part of Central Engineering business unit at Marvell, Bangalore. This team as part of global Implementation team plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation all custom ASICs for all the OEM s. We are looking for individuals with the domain of physical design having Block /Subsystem level implementation experience on hierarchical designs using industry standard tools. What You Can Expect Work with a global team on the physical design of complex chips at Block/Partition/Full-Chip level. You will also play a critical role in refining the methodology to enable an efficient and robust design process working closely with the methodology team. Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on a given hierarchical design at block/partition/full-chip level. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Collaboration with the frontend team will be crucial to ensure successful tapeouts. Additionally, your involvement with the global timing team will include debugging and resolving any block/partition level timing issues encountered at the Chip level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. What Were Looking For Have completed a Bachelor s OR a Masters Degree in Electronics/Electrical/VLSI field and have atleast 15+ years of related professional experience in physical design at Partition/Subsystem/Chip level with a proven track record of successful tape-outs. In your coursework, you must have completed a course in digital electronics, CMOS design and projects that involved circuit design & analysis. Good understanding of standard RTL to GDS flows and methodology, experience in designing ICs at advanced technology nodes (e. g. , 7nm, 5nm, or below) is highly desirable. Working knowledge on any of the scripting in languages such as Perl, tcl, AWK and Python. Knowledge of Verilog/VHDL basics is an added advantage. Good communication skills and self-discipline contributing in a team environment. In-depth knowledge and hands-on experience with industry-standard physical design tools and methodologies, including synthesis, floor planning, placement, clock tree synthesis, routing, and physical verification.

The Opportunity Were looking for the Wavemakers of tomorrow. What You ll Do SERDES sub-block design and technical leadership for clocking, TX, RX etc Define Block-level architecture and circuit topologies to meet system spec Circuit Design and simulation across PVT and sign off quality matrix to meet specs Mentor the junior designers and support them in problem solving Support .lib generation and Verilog modelling for block owned and validate with schematic Custom Layout guidelines and post-layout simulations Documentation, Review and Signoff on design What You ll Need Minimum 8+ years of experience in Analog circuit design from a reputed product-based company Previous experience of leading analog engineering design teams is must Experience in dual patterning FinFET design in in TSMC 3nm, 5nm etc Experience designing circuit at 56+ Gbps speed Understanding of device basics and physics High-speed Driver and Receiver designs, PLL design with solid system understanding BTech/MTech/MS in VLSI from a reputed university "We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

We have a new demand for a GFXIP Emulation Methodology Lead for our client AMD, located in Bangalore . This is a high-priority requirement, and we are looking for candidates who can join immediately or within 15 days . Key Responsibilities: Exposure to Emulation model build and sanity bring-up Proven Emulation Testbench bring-up experience with C++ and SystemVerilog BFM models Expertise in porting C++/SystemVerilog Simulation Testbenches to Emulation Hands-on experience with SystemVerilog, C++ based testbenches BFM coding using C++ or SystemVerilog Strong Python scripting skills Exposure to GPU emulation model build and sanity bring-up Good understanding of GPU architecture Strong functional verification expertise Qualifications: B.Tech with 12+ years or M.Tech with 10+ years in Electronics and Communication Engineering (ECE) or VLSI

Alphawave Semi is looking for Senior Engineer I - ASIC Design to join our dynamic team and embark on a rewarding career journey. Analyze and assess problems. Apply quality principles and methodology in processes to enhance output. Assess new product designs to meet project and product requirements. Create engineering designs. Identify the design needs of clients. Manage disputes and conflicts. Manage product design and development to meet project and product requirements. Oversee Workplace Safety and Health Systems (WSH) for the company.

The Opportunity Were looking for the Wavemakers of tomorrow. What Youll do: Responsible for front end implementation of IPs which includes Synthesis, LEC, CLP. Collaborate with designers and PNR teams to achieve design closure with focus on Quality Ability to debug and resolve technical issues. Hands on functional ECO generation using Candence conformal LEC Should be able to provide good support to Gate level simulations (GLS) team Overall, should have good knowledge on RTL so as to understand all synthesis related warnings. What Youll Need: 5-7 years experience in physical aware synthesis. Self-motivated complete understanding of timing constraints, low power aspects and concepts of DFT Experienced in synthesis, LEC, CLP and timing closure Should have handled blocks with complex designs, multiple high frequency clocks and complex clocking. scripting and automation experience is a must. We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Hiring for Freshers Desingnation:- Technical Support Engineer - VLSI Work Mode: WFO (6 days) No.of positions: 10 Experience: 0 - 1 years Education: BE/BTech/MTech/ECE/EEE in VLSI Industry Type: Education / E-Learning / Semiconductor Filter: Full- time- Work from Office Stipend: 15k - 20k Role & responsibilities Responsible for development and support of Projects. Responsible for debugging the source codes in Verilog, SV, and UVM. Responsible for Monitoring the trainee's progress. Will be a point of contact for trainees to query on Technical concepts. Preferred candidate profile Sound Knowledge on Verilog, SV, Digital ,UVM / Back-end design Good communication skill. Should be good in Digital Electronics.

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-6years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug