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10.0 - 15.0 years

35 - 40 Lacs

Bengaluru

Work from Office

Title: Standard Cell Layout Design About GLOBALFOUNDRIES GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com . Introduction In this position you will be integrated in our Foundry IP Development team in Bangalore. In close collaboration with other disciplines across our worldwide engineering teams you will be developing layout for Std cell IP which enable our customers to perform product designs at highest quality standards based on Globalfoundries advanced process nodes. Job Responsibilities The development of product grade Standard Cell IP covering the following phases: Layout Design of Standard Cell IPs Layout checks like LVS, DRC, DFM, EMIR Review of Layouts and extend help for other Layout teams Design Kit prep from layout side, verification and validation Layout automation and script support Being a good team player, taking key initiatives for productivity improvements and innovation Sign off and release into dedicated IP validation test chips Specification and documentation Support of silicon bring up and characterization Required Qualifications: Bachelor s degree with 10+ years or master s degree with 8+ years experience in semiconductors / Microelectronics / VLSI engineering. Practical experiences in Standard Cell layout design in one or several of the following areas: Layout design and optimization of Combinational and Sequential Cells for various drive strengths and topology options. Layout design of Power Management Kit cells like Level Shifter, Power Gating, Isolation and Always-on Cells. Layout Architecture design for Ultra High Density and High-Performance Libraries. Layout design of custom cells to meet specific low power or high-speed design requirements. Proficient in handling EDA tools from Synopsis, Mentor and Cadence used for layout design like schematic/layout editor, parasitic extraction tools, DRC, LVS, DFM, EMIR, etc. Basic understanding of fabrication steps and flow. Experience in Testchip integration and analysis will be an added advantage. Preferred Qualifications: Good knowledge of CMOS technology Hands-on knowledge of state-of-the-art standard cell layout flows Programming experience applicable to design flow automation tasks The ability to work within a very dynamic interdisciplinary environment as well as dedicated knowledge of 45/32/28nm and below technology nodes are an advantage. You are flexible, highly motivated and have a team-oriented working style. You have shown the ability to communicate as well as work efficiently in an international multi-disciplinary environment. Strong written and verbal communication skills in English are a must. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

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12.0 - 16.0 years

9 - 13 Lacs

Bengaluru

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In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running.The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise Join Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, weve united two industry leaders to create an optical networking powerhousecombining cutting-edge technology with proven leadership to redefine the future of connectivity. Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group. As an FPGA Verification engineer, you will be responsible for designing verification plans, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up to ensure first time right quality of Infinera product. Candidate should be capable of handling projects independently and have a strong will to drive for solutions. Must have 12 16 yearsof experience in developing System Verilog UVM based test environments, developing and implementing test plans at block, sub-chip and chip levels. Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform-based debugging tools. Exposure to UVM (or similar) verification methodologies is required. Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. Working knowledge of RTL design is preferred. Should be conversant with technologies like the Ethernet, PCIe, I2C, SPI etc. Knowledge of telecom protocol is preferred. Structured and thorough with analytical and troubleshooting skills. Good written and oral communication skills are required. Flexible, innovative, self-driven and willing to take initiatives. Highly motivated team player with exceptional leadership capability. Develop and execute verification plans for high-complexity DWDM systems used in LH/ULH optical network applications. Design and implement simulation environments and testbenches to validate FPGA functionality and performance. Create and run functional and directed/random test scenarios to ensure comprehensive design coverage. Perform detailed coverage analysis and implement strategies to achieve full functional and code coverage. Collaborate closely with cross-functional R&D teams across multiple global locations throughout the product lifecycle. Provide lab support during board bring-up and assist in root cause analysis to ensure first-time-right product quality. Independently manage verification projects with a proactive and solution-driven approach to meet quality and timeline goals.

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15.0 - 25.0 years

10 - 14 Lacs

Chennai

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Job description For Electronics and Communication Engineering Program: Teaching Research experience in the following areas Robotics/Artificial Intelligence/Machine Learning/Data Science/Signal Processing / VLSI / Embedded Systems / Internet of Things / Nano Materials / Sensors / Quantum Computing / Data Structures and Algorithms / Computer Vision / AI, ML, DL / Image Processing / Cyber-Physical Systems / Wireless Sensor Networks / Next Generation Wireless Technologies / Intelligent Systems. Skill Required Robotic System Development and Programming Architecture, ROS MATLAB, Keil, Cadence tool, Xilinx Vivado, Microwave Studio, Python, Embedded C. The candidate should have adequate experience in research in their area of specialization, publications in top-tier journals, sponsored research, patent publication, and industry consultancy.

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0.0 - 5.0 years

32 - 40 Lacs

Hyderabad, Bengaluru

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NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It s a unique legacy of innovation that s fueled by great technology and amazing people. Today, we re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what s never been done before takes vision, innovation, and the world s best talent. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are now looking for RTL Design engineers for our Security Subsystem Design deployed in Automotive, GPU, DPU and Client chips. As one of the primary designers, you will be responsible for Security cluster of next generation chips. One should possess strong digital design and verification fundamentals. What youll be doing: As a senior designer, be responsible for understanding system security concepts and features, make architectural trade-offs based on feature/performance/power requirements, analyze system implications, come up with the micro-architecture, implement RTL, drive the verification, close timing, and support silicon validation. During the course of a project you would end up driving the following aspects of design for your unit: Own micro-architecture and RTL development of design modules Micro-architect features to meet performance, power and area requirements Work with HW architects to define critical features Partner with verification teams to verify the correctness of implemented features Work with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. What we need to see: You should be BTech/MTech having a proven track record in crafting complex Units and CPU/micro-controller based Sub-systems 2 + years of design experience Knowledge of security standards, protocols and system security architectures of modern SOCs would be a significant plus Excellent influencing skills resulting in collaboration with cross-cultural, multi geography and matrixed teams Good debugging, analytical and problem solving skills Great interpersonal skills and ability to work as an excellent teammate We have some of the most brilliant and talented people in the world working for us. If youre creative and independent, with a genuine real passion for technology and improving the state of art, we want to hear from you! Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www. nvidiabenefits. com/ #LI-Hybrid

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8.0 - 13.0 years

25 - 30 Lacs

Hyderabad

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At Micron, we transform how the world uses information to enrich life for all. The pace is fast, collaboration occurs on a regular basis, and innovation is expected. As a test platform development Engineer within the Non-Volatile Engineering (NVEG) Product Engineer team, you will develop and qualify low-cost in-house engineering test platforms and solve complex problems. This role requires deep understanding of test hardware and software along with NAND, UFS and PCIe protocol knowledge. You will be responsible to enable the PE test infrastructure and test platforms to test, debug and characterizing the NAND component and System products by closely working with the cross functional teams such as Test Engineering and System Integration, ASIC and FW teams and assist Qualification and Ramping of cutting-edge NAND and System Micron products. The candidates responsibility is to design, develop, debug and optimize the firmware for the test platform. Key Responsibilities: Design, develop, and qualify product engineering test hardware, platforms, test firmware and software for non-volatile memory product bring up and debug. Design, develop, debug, validate and optimize firmware code for products. Collaborate with cross-functional teams, including Test Engineering & System Integration, ASIC, FW, Product Engineering and operations, to integrate FPGA designs with other system components. Provide engineering test solutions (HW & SW) for Product Development for NAND/System characterization and Silicon debug capabilities Drive and support new protocol enablement (SCA- Separate Command Address, ONFI, UFS, PCIe) and capability bring up Routinely communicate overall project status to leadership and cross functional product team Provide guidance through debug and resolution of product related issues Qualifications: Successful candidates for this exciting opportunity will have: 8+ years of strong hands-on experience working on firmware development using C/C++ and good understanding of scripting languages including TCL, Perl/Python. Proficiency with GNU toolchain to compile, debug and build software applications. Experience in embedded systems, and good understanding of low-level firmware architecture. Knowledge of the entire firmware development lifecycle from requirements analysis, design, testing and maintenance. Knowledge of storage interface such as High Speed ONFI, UFS, PCIe, etc. Memory and Storage System behavior, architecture and design Working experience on NAND and non-volatile System products Experience with non-volatile memory, logic analyzers, oscilloscopes, and/or Automated Test Equipment (ATE) is preferred Familiar working on Unix/Linux terminal. Hands-on experience with hardware bring-up and debugging and understanding of hardware schematic and layout. Excellent data analysis, problem solving, and decision-making skills Ability to work independently in a very fast paced environment and adapt to change Drive to determine root-cause and provide corrective action for product issues Proficiency in using version control systems like Git for managing code repositories and collaboration. Self-motivated and enthusiastic in a challenging, dynamic environment Demonstrated ability to partner successfully with other groups to build strong peer relationships and achieve the best outcomes for Micron Education: Position requires a minimum of a Bachelors degree in Electrical, Electronics or Computer Engineering Course work in VLSI, semiconductor process is desirable, but not required To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidates true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

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5.0 - 15.0 years

35 - 40 Lacs

Hyderabad

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MTS SILICON DESIGN ENGINEER THE ROLE: The verification team at AMD is looking for a Member of Technical Staff to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs. THE PERSON: You have a passion for modern, complex digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications Interact with architects and design engineers to create a comprehensive verification testplan Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools Debug tests with design engineers to deliver functionally correct design blocks Identify and write coverage measures for stimulus quality improvements Perform coverage analysis to identify verification holes and achieve closure on coverage metrics PREFERRED EXPERIENCE: Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs. Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification. Strong understanding of different phases of ASIC and/or full custom chip development is required. Experience in block level NOC (Net work on Chip) verification is a plus. Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus. Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus. Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus. Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

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6.0 - 11.0 years

8 - 13 Lacs

Hyderabad

Work from Office

At Micron, we transform how the world uses information to enrich life for all. The pace is fast, collaboration occurs on a regular basis, and innovation is expected. As a test platform development Engineer within the Non-Volatile Engineering (NVEG) Product Engineer team, you will develop and qualify low-cost in-house engineering test platforms and solve complex problems. This role requires deep understanding of test hardware and software along with NAND, UFS and PCIe protocol knowledge. You will be responsible to enable the PE test infrastructure and test platforms to test, debug and characterizing the NAND component and System products by closely working with the cross functional teams such as Test Engineering and System Integration, ASIC and FW teams and assist Qualification and Ramping of cutting-edge NAND and System Micron products. The candidates responsibility is to design, develop and debug the VHDL or Verilog based application and have good knowledge of FPGA platform development lifecycle. Key Responsibilities: Design, develop, and qualify product engineering test hardware, platforms, test firmware and software for non-volatile memory product bring up and debug. Develop efficient RTL design using Verilog or VHDL for FPGA implementation, ensuring optimal resource utilization. Drive complete FPGA design flow including synthesis, place and route, timing analysis and verification. Implement FPGA designs on hardware platforms using tools like Xilinx Vivado and optimize for performance, area and power and to create test bench and verification scripts. Debug and validate FPGA designs in hardware using tools such as oscilloscopes , logic analyzers , and signal tap . Optimize designs for speed, power, and resource usage based on the specific FPGA platform used. Collaborate with cross-functional teams, including Test Engineering & System Integration, ASIC, FW, Product Engineering and operations, to integrate FPGA designs with other system components. Provide engineering test solutions (HW & SW) for Product Development for NAND/System characterization and Silicon debug capabilities Drive and support new protocol enablement (SCA- Separate Command Address, ONFI, UFS, PCIe) and capability bring up Routinely communicate overall project status to leadership and cross functional product team Provide guidance through debug and resolution of product related issues Qualifications: Successful candidates for this exciting opportunity will have: 6+ years of experience in RTL design, synthesis, timing closure, and verification methodologies. Knowledge of storage interface such as High Speed ONFI, UFS, PCIe, etc. Memory and Storage System behavior, architecture and design Working experience on NAND and non-volatile System products Experience with non-volatile memory, logic analyzers, oscilloscopes, and/or Automated Test Equipment (ATE) is preferred Experience working on firmware development using C/C++ and good understanding of scripting languages including TCL, Perl/Python. Familiar working on Unix/Linux terminal. Hands-on experience with hardware bring-up and debugging and Understanding of hardware schematic and layout. Excellent data analysis, problem solving, and decision-making skills Ability to work independently in a very fast paced environment and adapt to change Drive to determine root-cause and provide corrective action for product issues Self-motivated and enthusiastic in a challenging, dynamic environment Demonstrated ability to partner successfully with other groups to build strong peer relationships and achieve the best outcomes for Micron Education: Position requires a minimum of a Bachelors degree in Electrical, Electronics or Computer Engineering Course work in VLSI, semiconductor process is desirable, but not required To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidates true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

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0.0 years

4 - 8 Lacs

Bengaluru

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This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers. Skills (competencies)

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5.0 - 10.0 years

8 - 18 Lacs

Bengaluru

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• Experience with EDA tools associated to Analog front-end from Cadence • Analog circuit design and simulations • Put in place new design/technology porting flows (using different EDA tools)

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5.0 - 10.0 years

15 - 17 Lacs

Hyderabad

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Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualification BE/BTech from any reputed University Masters Preferred Experience Between 3 to 10 years Hands on with any of the spice simulators (Hspice/ Spectre)

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8.0 - 13.0 years

25 - 35 Lacs

Bengaluru

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MTS GFX Design Role: We are currently seeking a highly skilled design engineer for GFX Design team. Responsibilities: In this role, he/she would be responsible for verification of GPU Design by meeting the demands of the constantly evolving project schedule. The successful candidate will be a member of the GFX team. He/she will demonstrate passion towards design, design verification, be a teammate, a problem solver with independence, creativity, and interpersonal skills. Working with all partners such as lead architects and block design teams to understand features to be implemented and verified. Developing robust test plan for both synthetic testing and real workload trace Debug verification test failures, working with the verification team to accurate defects. Make sure AMD next generation GFXIP can meet performance/power/function expectation. Requirements: Must have Min 8 years of experienced in ASIC verification. Must be proficient in Verilog and System Verilog language Must be good at optimizing timing in digital design. Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation/emulation tools and develop optimal microarchitecture specification that meets PPA goals. Be proficient of script language like Perl, Python. Must demonstrate strong analytical thinking and problem-solving skills with an excellent attention to detail. Must have good English hearing, speaking, reading, and writing capabilities. Must have good teamwork and interpersonal skills. Graphics pipeline experience is preferred. Good knowledge of computer architecture is preferred. Must be a self-starter, and able to independently drive tasks to completion. Good teamwork and communications skills are required. Academic credentials: B.E/B.Tech or M.E/M.Tech degree in ECE/ Electrical Engineering / Computer Engineering with Digital Systems/VLSI as major with 8+ Years of Exp Location: Bangalore, India #LI-NS1 Benefits offered are described: AMD benefits at a glance .

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3.0 - 4.0 years

5 - 10 Lacs

Noida

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Requisition #: 16946 Our Mission: Powering Innovation That Drives Human Advancement When visionary companies need to know how their world-changing ideas will perform, they close the gap between design and reality with Ansys simulation. For more than 50 years, Ansys software has enabled innovators across industries to push boundaries by using the predictive power of simulation. From sustainable transportation to advanced semiconductors, from satellite systems to life-saving medical devices, the next great leaps in human advancement will be powered by Ansys. Innovate With Ansys, Power Your Career. SUMMARY The engineer will join the PowerArtist Elaboration and PDB team. He/she will develop features and algorithms for the power analysis tool (PowerArtist) in area of Elaboration and/or Power-Database (PDB) using C++ language on Linux platform. He/she will be expected to write test cases for the features developed and assigned to him/her to increase the robustness of the tool. RESPONSIBILITIES Learn the team s software development processes. Diagnose and fix code problems. Deliver code and scripts that meet requirements on schedule. Ensure that code is efficient, scalable, maintainable, extensible, robust and easy to understand. Create unit, regression and/or system-level tests to thoroughly validate new features or changes. Communicate clearly and work closely with the team to refine solutions and to describe changes that may affect others. Learn and follow best practices in software engineering. MINIMUM QUALIFICATIONS B.E./BTech. or M.E./MTech. degree in Electronics Engineering, Computer Science, or related field like VLSI Working knowledge in C or C++ Working knowledge of the Linux operating system Strong basic knowledge of data structures, algorithms. Debugging skill is a plus. Ability to learn quickly, understand complex systems and to work closely with others Ability to complete high-quality work on time PREFERRED QUALIFICATIONS Some exposure to EDA domain technologies. At Ansys, we know that changing the world takes vision, skill, and each other. We fuel new ideas, build relationships, and help each other realize our greatest potential. We are ONE Ansys. We operate on three key components: our commitments to stakeholders, our values that guide how we work together, and our actions to deliver results. As ONE Ansys, we are powering innovation that drives human advancement Our Commitments: Amaze with innovative products and solutions Make our customers incredibly successful Act with integrity Ensure employees thrive and shareholders prosper Our Values: Adaptability: Be open, welcome what s next Courage: Be courageous, move forward passionately Generosity: Be generous, share, listen, serve Authenticity: Be you, make us stronger Our Actions: We commit to audacious goals We work seamlessly as a team We demonstrate mastery We deliver outstanding results VALUES IN ACTION Ansys is committed to powering the people who power human advancement. We believe in creating and nurturing a workplace that supports and welcomes people of all backgrounds; encouraging them to bring their talents and experience to a workplace where they are valued and can thrive. Our culture is grounded in our four core values of adaptability, courage, generosity, and authenticity. Through our behaviors and actions, these values foster higher team performance and greater innovation for our customers. We re proud to offer programs, available to all employees, to further impact innovation and business outcomes, such as employee networks and learning communities that inform solutions for our globally minded customer base. WELCOME WHAT S NEXT IN YOUR CAREER AT ANSYS At Ansys, you will find yourself among the sharpest minds and most visionary leaders across the globe. Collectively, we strive to change the world with innovative technology and transformational solutions. With a prestigious reputation in working with well-known, world-class companies, standards at Ansys are high met by those willing to rise to the occasion and meet those challenges head on. Our team is passionate about pushing the limits of world-class simulation technology, empowering our customers to turn their design concepts into successful, innovative products faster and at a lower cost. Ready to feel inspired? Check out some of our recent customer stories, here and here . At Ansys, it s about the learning, the discovery, and the collaboration. It s about the what s next as much as the mission accomplished. And it s about the melding of disciplined intellect with strategic direction and results that have, can, and do impact real people in real ways. All this is forged within a working environment built on respect, autonomy, and ethics. CREATING A PLACE WE RE PROUD TO BE Ansys is an S&P 500 company and a member of the NASDAQ-100. We are proud to have been recognized for the following more recent awards, although our list goes on: Newsweek s Most Loved Workplace globally and in the U.S., Gold Stevie Award Winner, America s Most Responsible Companies, Fast Company World Changing Ideas, Great Place to Work Certified (China, Greece, France, India, Japan, Korea, Spain, Sweden, Taiwan, and U.K.). For more information, please visit us at www.ansys.com Ansys is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, and other protected characteristics. Ansys does not accept unsolicited referrals for vacancies, and any unsolicited referral will become the property of Ansys. Upon hire, no fee will be owed to the agency, person, or entity.

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3.0 - 5.0 years

0 - 0 Lacs

Noida, Bengaluru

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Role & respon Responsibilities: Develop business accounts and customer projects, prepare strategies for sales, well position Product in front of customer. Reach out and do follow ups with customers from a variety of marketing campaigns to qualify potential business leads. Research targeted companies/contacts to position company products. Send personalized emails and make outbound calls to targeted accounts and contacts. Provide Project Managers with solid prospect background on opportunities to ensure high-quality prospect transition into the sales process. Execute the necessary daily activities to meet your weekly/monthly goals. Track all activity thoroughly in our CRM system to support account and management teams. Qualification: Developing business and building relationships over phone and email, with excellent interpersonal, verbal and written capabilities in English (professional proficiency) Flexible with working timing. Preferred candidate profile REQUIREMENT : Knowledge of VLSI is mandatory either frontend or backend. 4-5 years of relevant experience in the semiconductor industry (understand Chips and IPs, ASIC Design Flow etc.) Proven experience in Marketing and Sales within the semiconductor domain. Working knowledge of EVK's (Evaluation kit) Working knowledge of BLE, BT, wifi etc. Having experience of any of the chipset like - ST micro . Excellent verbal communication and listening skills. sibilities

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6.0 - 11.0 years

8 - 12 Lacs

Ranchi

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We are looking for a skilled Delivery Ops Lead - IT Staffing with 6 to 12 years of experience in IT staffing and recruitment. The ideal candidate will have a strong background in managing teams and delivering results-driven solutions. This position is based in Ranchi, Noida, or remotely from Bengaluru. Roles and Responsibility Manage and lead a team of recruiters specializing in IT staffing, focusing on roles such as Cloud Architecture, Data Science, SAP, IDMC, Data Bricks, and more. Perform extensive calling and vetting of profiles to ensure alignment with client requirements. Manage end-to-end recruitment processes, from sourcing to placement, ensuring high-quality candidates are provided. Utilize ATS (Applicant Tracking System) and various job portals to source candidates effectively. Leverage headhunting techniques to find and recruit top talent for niche skill sets. Screen and evaluate candidates to ensure they meet the required qualifications and experience for each role. Foster a collaborative work environment with clients and internal teams to ensure seamless recruitment operations. Ensure excellent communication with clients, candidates, and internal teams for smooth coordination throughout the hiring process. Job Minimum 6 years of experience in IT staffing and recruitment across various domains. In-depth knowledge of Cloud Architecture, Data Science, SAP, IDMC, Data Bricks, Embedded/VLSI, and other related technologies. Proven track record of managing and mentoring a team in the domestic IT staffing domain. Excellent communication, interpersonal, and organizational skills. Experience working with ATS and various recruitment portals. Strong experience in headhunting and sourcing for specialized IT roles. Ability to handle a fast-paced work environment and meet recruitment targets effectively. Previous experience working in the Cloud, SAP, Embedded/VLSI, and Data Science domains is preferred. Hands-on experience with IT staffing tools and platforms. Strong team management experience with a results-driven approach.

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5.0 - 7.0 years

6 - 10 Lacs

Ranchi

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We are looking for a skilled Senior IT Recruiter with 5 to 7 years of experience in IT recruitment, specifically within domains such as Cloud Architecture, Data Science, SAP, IDMC, Data Bricks, VLSI/Embedded, and other technical roles. The ideal candidate will have a strong background in managing both subcontracting and full-time employee models. Roles and Responsibility Lead end-to-end recruitment processes for various IT roles, focusing on Cloud Architecture, Data Science, SAP, IDMC, Data Bricks, VLSI/Embedded, and other technical roles. Conduct extensive calling and profile screening to ensure the best fit for client requirements. Utilize Applicant Tracking Systems (ATS) and other portals to source, manage, and track candidate pipelines effectively. Perform headhunting to identify and engage passive candidates for specialized roles. Manage both subcontracting and full-time employee models for IT staffing. Ensure successful closures and meet recruitment targets by understanding client needs and delivering the right candidates. Job Minimum 5 years of experience in IT recruitment, preferably in Cloud Architecture, Data Science, SAP, IDMC, Data Bricks, VLSI/Embedded, or other technical roles. Strong experience working in IT staffing for both subcontracting and full-time employment models. Proficiency in ATS systems and various recruitment portals is required. Headhunting skills for identifying and sourcing niche talent are essential. A strong understanding of GSI accounts and their recruitment requirements is necessary. Proven track record of meeting recruitment targets and successfully closing positions. Excellent communication skills are needed to engage with candidates, clients, and internal teams. Knowledge of the latest trends in IT staffing and technology recruitment is expected.

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15.0 - 20.0 years

15 - 20 Lacs

Bengaluru

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Bachelors/Masters degree in Electronics Telecommunication/ Electrical engineering (VLSI Design) Extensive Hands-on CAD Tools experience (Layout (backend), Design automation tools) 15+ years of Experience in CAD Tools, automation (Skill, perl, Python etc) Expertise in working with Layout, Design Teams to build and deploy CAD solutions > 3 to 5 years Management experience to handle Team of CAD engineers Experience in working with cross geo, cross team functions and stake holder management Strong communication skills circuit design knowledge is preferred. Tool knowledge: EDA Tools (Synopsys, Cadence, Calibre tools and other CAD tool vendors) Expertise and knowledge of Layout flows DRC/LVS/ERC, Design flows : Spice (finesim, hspice), EM, IR drop analysis, ESD tools Qualifications B.TECH/M.TECH in Electrical / Electronics / VLSI / Microelectronics with 15+ years of experience

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1.0 - 3.0 years

7 - 8 Lacs

Bengaluru

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Experience in dft scan insertion, atpg at ip and soc level Hands on experience in atpg timing and no-timing simulations Proficient in doing basic unit-level verification using simulations. Scan/atpg patterns & test flows development, debug, test and characterization

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5.0 - 10.0 years

8 - 13 Lacs

Bengaluru

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Experienced in rtl design using verilog / system Verilog Asic designers with experiences in all aspects of rtl design flow from specification/microarchitecture definition to design and verification, timing analysis, dft and implementation Integration, rtl signoff tools, upf/low power signoff and cdc/rdc, lint Strong domain knowledge of clocking, system modes. Power management, debug, interconnect, safety, security and other architectures

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1.0 - 5.0 years

3 - 7 Lacs

Hyderabad

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To create a project in compliance with Industrial Standards(ARP4761, ISO26262, MIL-Std 882E, etc.) To perform safety analysis like FMEA, FTA, RBD, Safety Cases, FHA etc. To perform activities, engineer can be placed onsite at customer location/in-office Requirements B.E/B.Tech (Electronics, EEE, ECE , E&I )Basic knowledge on Analog & Digital Electronics, VLSI etc. Experience required - Fresher Base Location - Hyderabad (but should be ready to travel & deployed across India)

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8.0 - 12.0 years

9 - 13 Lacs

Noida

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Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Position presents an opportunity to join the award winning and market leading Tessent team, India. The focus of the role is advanced design-for-test (DFT) insertion and automatic test pattern generation (ATPG) for semiconductor designs. It will involve understanding and supporting the latest DFT ATPG electronic design automation (EDA) technologies such as Tessent TestKompress and Streaming Scan Network (SSN). Someone in this role will gain a deep understanding of scan design, on-chip clock controls, and IJTAG infrastructure in support of scan testing. They will support the worldwide application engineering team on complex ATPG issues and build testcases for advanced DFT methodologies. This role is based in Noida. But youll also get to visit other locations in India and globe, so youll need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. Responsibilities for this role include: Build and deliver in-depth technical presentations, develop training material, white papers, supplied articles, and application notes. Work with customers as well as Siemens stakeholders such as regional application engineers, global support engineers, and marketing. Are you expertized in working through complex technical issues and independently building solutions and new methodologies! Explain complex principles in simple terms to broad audiences. Some travel, domestic and international. Successful deployment of existing and new Tessent DFT products in customer designs by enabling AEs. Working closely with our key customers on deployment challenges. Working with PEs and R&D to ensure new product readiness testcase in form of testcases, documentation and trainings. Architecture reviews of customer designs. Closely working with AEs to gather top issues blocking their engagement's success. Deep learning opportunities for Tessent DFT products including opportunities to present at various conferences worldwide including ITC and Siemens U2U. We dont need hard workers, just superminds! BS degree (or equivalent) in Electrical Engineering, Computer Science or related field is required with 8 - 12 years of experience. Knowledge of design logic design languages, tool usage, design flow steps required. We are looking for someone that has exposure to DFT or SoC design for complex ASICs / SOCs. ATPG, IEEE 1687 IJTAG, boundary scan (BSCAN), hierarchical DFT implementation. Knowledge of a scripting language like TCL. We need someone self-motivated and dedication to improvement with strong problem-solving skills. Excellent organizational skills, written and verbal English language communication skills. Proficiency in LINUX and Windows environments. The role presents many opportunities to build specialized DFT and ATPG knowledge. Publications and other promotions of methodologies is encouraged. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! Transform the everyday #LI-EDA #LI-HYBRID

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4.0 - 9.0 years

12 - 17 Lacs

Bengaluru

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Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Job Responsibilities Responsible for Corporate Application Engineering (CAE) activities in the Design for Test (DFT) Domain of VLSI systems From a technical stand-point, understanding customer needs on DFT, involve and work with their projects for using right methodologies and Siemens tools for successful project completion Provide DFT Tool support to all the existing customers. Help customers improve the productivity through efficient tool usage. Provide onsite tool support to customers as and when needed Developing and delivering technical training on new features and product updates Tracking and updating customer issues using defined Siemens processes and tracking tools. Developing Technical content for Siemens knowledgebase. Involve and drive the Tool evaluation/benchmark; Technical product presentations; Methodology review; Tool deployment and adoption; drive competitive replacements, provide support to customers during critical project implementation phases. Educational qualifications: Required BE/B.Tech in Electronics & Communications Engineering (E&C), or Electrical and Electronics Engineering (EEE) Work Experience: 4+ years relevant experience in DFT area of VLSI domain. Technical skills: In additional to possessing hands-on knowledge of DFT implementation and verification, the position would need excellent problem solving & communication skills able to work independently to solve complex problems and device new solutions and workarounds for customer issues. Knowledge and experience with VLSI design, HDL Synthesis, VLSI Testing and design for testability. Experience with design, simulation, verification of ASIC/VLSI circuits and systems, design verification and product test generation preferred. In-depth understanding of Design for Test (DFT) structures is required. This includes ATPG/Scan/Compression based testing, Memory BIST, Logic BIST, IJTAG and Boundary Scan (1149.1/6). Knowledge of scan data compression methodologies with EDT is preferred. Preferred experience in specific areas: Operating SystemsUNIX, Linux, Sun Solaris. LanguagesVerilog (Behavioral, RTL, gate level), VHDL (Behavioral, RTL, gate level), Perl, C/C++. CAD ToolsSynthesis, Simulation, ATPG, Memory BIST, Logic BIST, Boundary Scan. Familiarity with Tessent flows and methodologies is a plus. General/soft skills: Work effectively with customers, internally with divisions and R&D Ability to work autonomously Strong verbal and written communication skills; good presentation skills Excellent organizational and time management skills Build and foster relationships with customer and peers with a positive attitude to win business success Good problem solving and debugging skills, Willingness for technical sales Should be a good team player Job may require some domestic and international travel. #DISW #LI-EDA #LI-Hybrid A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! At Siemens, we are always challenging ourselves to build a better future. We need the most innovative and diverse Digital Minds to develop tomorrows reality. Find out more about the Digital world of Siemens here:/digitalminds Siemens Software. Where today meets tomorrow

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12.0 - 17.0 years

6 - 10 Lacs

Bengaluru

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-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -12+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

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3.0 - 8.0 years

8 - 11 Lacs

Bengaluru

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We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering & Electronics & Communication Engineering ready to handle the challenging problems in future technologies and designs. We are also looking for candidates with Machine Learning/AI and/or Data Science background to lead our leading-edge algorithms and AI technology within our EDA solutions to increase our design team’s productivity and chip quality and performance. Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world. We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Strong interpersonal skills are needed to coordinate deliverables and requirements from several areas within and outside of the organization.There are many opportunities to gain and utilize a deep understanding of future issues and provide input towards decisions affecting system development, logical and physical design as well as sophisticated methodology directions. Individuals who are chosen to become a part of our world class development teams will be helping advance IBM’s leadership in developing the highest performing computers and changing hardware solutions. Do you want to be an IBMerCome THINK with us! Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Individual contributor for Gate Leve Sign off Timing team to work on ASICs or Server Timing Methodology. 3+ years of Semiconductor/VLSI experience Proven problem-solving skills and the ability to work in a team environment are a must EDA Tool/Methodology development experience Thorough understanding of Static Timing Analysis. Knowledge of other VLSI domains is a plus Excellent scripting skills - TCL/Python/Shell Preferred technical and professional experience Cadence tools, Synopsys tools, VLSI knowledge, VHDL/Verilog, computer architecture, Machine Learning/AI

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4.0 - 9.0 years

10 - 20 Lacs

Bengaluru

Work from Office

Role & responsibilities Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com call me :7995220108. Client Name: Proxelera Position Name VLSI MBIST Engineer Position type: Permanent Total Exp: 4-8 years HBTS Budget: Open Notice Period: Immediate to 15days Work Location: Bangalore South Job Description Must have: We are seeking a skilled VLSI MBIST Engineer with approximately 4 years of experience, specialized in Memory Built-In Self-Test (MBIST) methodologies. The ideal candidate will have hands-on experience with Synopsys SMS tool and be proficient in MBIST pattern generation, fault simulation, and test development for various embedded memories in ASIC/SoC designs. Requirements Key Responsibilities: Develop and implement MBIST algorithms and test patterns for embedded memories (SRAM, DRAM, ROM, CAM) using Synopsys SMS tool. Create MBIST test infrastructure and collaborate with design teams to integrate MBIST macros into SoC designs. Perform fault modeling, fault simulation, and analysis to ensure high fault coverage and test quality. Validate MBIST patterns through simulation and silicon validation. Debug MBIST failures at both pre-silicon and post-silicon stages and provide root cause analysis. Work closely with RTL designers, physical design, and test teams to optimize MBIST architecture and test flows. Generate MBIST test reports, documentation, and provide design-for-test (DFT) reviews. Stay updated with latest MBIST methodologies and industry trends. Required Skills & Qualifications: Bachelors/Master’s degree in Electronics, Electrical Engineering, VLSI, or related field. Minimum 4 years of experience in MBIST engineering for ASIC/SoC designs. Strong knowledge of MBIST architectures, memory testing algorithms, and fault models. Hands-on experience with Synopsys SMS tool for MBIST pattern generation and validation. Familiarity with other DFT tools and methodologies is a plus. Proficient in scripting languages such as TCL, Perl, or Python for automation of MBIST flows. Good understanding of digital design and RTL coding (Verilog/SystemVerilog). Experience with simulation tools (ModelSim, VCS, etc.) and testbench development. Strong analytical and problem-solving skills with attention to detail. Good communication skills and ability to work in a team environment. Preferred Skills: Experience with other memory test tools or DFT tools like Tessent. Knowledge of ATPG and other DFT methodologies. Exposure to silicon bring-up and failure analysis. Familiarity with industry standards such as IEEE 1149.1 (JTAG), IEEE 1500. AMD (Don’t Share AMD Profiles) Preferred candidate profile

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4.0 - 9.0 years

12 - 22 Lacs

Bengaluru

Work from Office

Job Description: Understand customers requirements /specifications /tender enquiry. Define DSP, System and Board architecture. Project ownership from concept to delivery. This includes identifying risks, dependencies, creating mitigation plan, tracking project schedule, discussions with customers, design reviews. Partition the algorithms for implementing in FPGA and/or in SW. Identify the building blocks & Signal Processing functions. Provide estimates on FPGA resources, computation bandwidth, and memory bandwidth. Create module level details from architecture, coding, simulation and perform peer reviews. Apply the methodologies for design, verification or validation. Define, create and maintain all project related documentation, especially design documents with detailed analysis reports. Provide support to customer during integration phases at test sites and support to production teams. Defining the architecture of RTL functions HDL Coding Simulation and Implementation Testing on board and debugging Professional Skills: VHDL Knowledge Xilinx tools for synthesis and implementation Thorough understanding of Xilinx FPGAs Functional Simulation Hardware Design : Logic Design & Debugging expertise FPGA Design : VHDL/Verilog RTL Coding, System C/ System Verilog FPGA Synthesis & PAR Tools Implementing DSP algorithms in FPGA environment for Radar and Electronic Warfare systems. Modeling the algorithms in Octave/MATLAB, generating test vectors, visualizing data. Working knowledge on interfacing with ADCs and DACs and interpreting their performance. Fluency, good communication & presentation skills. Configuration/Version control tools like SVN

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