Field-Programmable Gate Arrays Engineer ACL Digital

1.0 - 3.0 years

0 Lacs

hyderabad, telangana, india

On-site

RTL-FPGA Engineer Location : Hyderabad Experience : 1-2 years understanding of Vivado Flow and HW validation using Xilinx(AMD) FPGAs. Strong understanding of FPGA flow using Vivado, Logic design, Digital design etc. . Expertise RTL Coding in Verilog / System Verilog or VHDL . Knowledge in Xilinx FPGA architecture Good Knowledge in Tcl or Python scripting

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Field-Programmable Gate Arrays Engineer ACL Digital

2.0 - 6.0 years

0 Lacs

hyderabad, telangana

On-site

As an FPGA / DV Engineer at ACL Digital in Hyderabad, you will be responsible for working on FPGA architecture, Vivado Flow, scripting and automation, Verilog/VHDL, and HW debugging. You should have a background in scripting and a conceptual understanding of Power. Key Responsibilities: - Work on FPGA architecture - Utilize Vivado Flow for development - Implement scripting and automation techniques - Write and debug Verilog/VHDL code - Perform hardware debugging tasks Qualifications Required: - 2-4 years of experience in FPGA design and verification - Proficiency in scripting languages - Strong conceptual understanding of Power - Knowledge of Verilog and VHDL programming - Ability to debug h...

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RTL FPGA Design Engineer ACL Digital

2.0 - 4.0 years

0 Lacs

hyderabad, telangana, india

On-site

RTL FPGA Design Engineer Experience : 2-4 years Location : Hyderabad FPGA architecture Vivado Flow Scripting and automation Verilog / VHDL HW debugging We are looking for some background of scripting and or conceptual understanding of Power for experienced candidates. Interested,please share your updated resume to [HIDDEN TEXT]

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