4.0 - 6.0 years

0 Lacs

hyderabad, telangana, india

On-site

About the Role We are looking for an experienced Analog Layout Engineer with strong hands-on exposure to TSMC advanced technology nodes . The candidate should have a solid understanding of full-chip and block-level layout for high-performance analog/mixed-signal IPs. Key Responsibilities Perform layout design for Analog, Mixed-Signal, and Custom circuits such as: PLL, LDOs, ADC/DAC, Bandgap, Amplifiers, High-Speed IO, SerDes blocks Execute layout of standard cells and custom leaf cells with best practices. Work on TSMC lower-node constraints including: Multi-patterning (DPT) FinFET layout rules Density rules EM/IR considerations Perform layout verification : DRC, LVS, ERC, Antenna, and Physi...

Posted 3 weeks ago

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Standard Cell Layout Design Engineer, Silicon Google

4.0 - 6.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 4 years of experience with layout design. Experience with library exchange format. Preferred qualifications: Master's degree in Electrical Engineering, Computer Science, or equivalent practical experience. Experience in coding and Unix shell scripting. Experience with Virtuoso XL and extraction tools such as Star-RC/QFS. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise wil...

Posted 3 months ago

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